Job description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s Intelligent Cloud mission. SCHIE delivers core infrastructure and foundational technologies supporting Azure, Microsoft 365, Teams, Xbox, and next-generation AI platforms at hyperscale, with a focus on high-quality, efficient, and trusted cloud hardware solutions. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Sr. Design Engineer – IP Office to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering team. Be a highly motivated self-starter with deep semiconductor IP development expertise who is excited to grow from technical leadership into program leadership. The role is responsible for driving cross-functional execution, managing risks and dependencies, ensuring high-quality IP delivery, and enabling successful product outcomes at scale. #SCHIE Responsibilities • Drive IP selection, qualification, and adoption for AI SoC programs, ensuring alignment with product requirements and SoC landing zones. • Lead IP acquisition (through IP license/SOW), release management, quality assurance, and integration of third-party and internal IPs. • Establish and scale robust processes for IP release, updates, QA, integration, and pre/post-silicon validation. • Track third-party and internal IP releases and updates, ensuring timely release of collaterals to internal SOC teams for integration and issue resolution. • Partner with Architecture, Design, Physical Design (PD), Design for Test (DFT), Validation, Packaging and Board Design teams to optimize design tradeoffs and drive integration quality reviews. • Drive cross-functional resolution of pre- and post-silicon IP issues and integration challenges. • Provide technical leadership through collaboration, influence, and effective stakeholder engagement across engineering organizations and vendors. Qualifications Required Qualifications: • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience Preferred Qualifications: • 4+ years of experience in Integration and debug of IPs in major CPU, GPU or AI accelerator SoC’s and close interactions with Major IP vendors and suppliers of SoCs • 4+ years Design experience either in IP development or in SoC level Integration of at least one of the following areas: • SRAM design, Register Files and Memory Compilers • High Speed serial and/or Parallel IOs • Sub-system and SoC integration • Detail understanding of IP collaterals required for front end, physical design and DFT integration into SOC • Track record of successful tape outs in deep sub-micron technologies • 2+ years of experience in IP office functions of a major CPU, GPU or AI SoC • Established reputation in interactions with leading suppliers of IPs in 112G/224G class Ethernet, PCIe 5/6, HBM3/4, temperature, voltage and process monitors • Scripting language such as Python or Perl • Knowledge of Front-end and back-end IP Integration flows in a SoC • Experience working with customers, external IP vendors and silicon foundry • Communication skills, self-motivation, and ability to collaborate with architecture, Front-end, Physical design and post-silicon teams in Microsoft Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

Drive IP selection, qualification, and adoption for AI SoC programs, ensuring alignment with product requirements and SoC landing zones.
Lead IP acquisition (through IP license/SOW), release management, quality assurance, and integration of third-party and internal IPs.
Establish and scale robust processes for IP release, updates, QA, integration, and pre/post-silicon validation.
Track third-party and internal IP releases and updates, ensuring timely release of collaterals to internal SOC teams for integration and issue resolution.
Partner with Architecture, Design, Physical Design (PD), Design for Test (DFT), Validation, Packaging and Board Design teams to optimize design tradeoffs and drive integration quality reviews.
Drive cross-functional resolution of pre- and post-silicon IP issues and integration challenges.
Provide technical leadership through collaboration, influence, and effective stakeholder engagement across engineering organizations and vendors.
4+ years of experience in Integration and debug of IPs in major CPU, GPU or AI accelerator SoC’s and close interactions with Major IP vendors and suppliers of SoCs
4+ years Design experience either in IP development or in SoC level Integration of at least one of the following areas:
Detail understanding of IP collaterals required for front end, physical design and DFT integration into SOC
2+ years of experience in IP office functions of a major CPU, GPU or AI SoC
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Nice-to-haves

SRAM design, Register Files and Memory Compilers
High Speed serial and/or Parallel IOs
Sub-system and SoC integration
Track record of successful tape outs in deep sub-micron technologies
Established reputation in interactions with leading suppliers of IPs in 112G/224G class Ethernet, PCIe 5/6, HBM3/4, temperature, voltage and process monitors
Scripting language such as Python or Perl
Knowledge of Front-end and back-end IP Integration flows in a SoC
Experience working with customers, external IP vendors and silicon foundry
Communication skills, self-motivation, and ability to collaborate with architecture, Front-end, Physical design and post-silicon teams in Microsoft

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

azureaipython

Platform: eightfold
Effort: medium