Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus Develop, maintain, and optimize physical verification flows for advanced node SoC’s. Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams Engage directly with foundry teams to resolve DRM ambiguities and waiver requests. Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows BASIC QUALIFICATIONS: Bachelor’s degree in electrical engineering, computer engineering or computer science 5+ years of ASIC and/or physical design flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation) Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.) Deep expertise in DRC, LVS, PERC and ESD verification methodologies Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus Direct foundry DRM experience — able to read, interpret, and implement complex rule decks Experience at advanced nodes (4nm and below) Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.) Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment ADDITIONAL REQUIREMENTS: Ability to work extended hours and weekends as needed to meet critical project milestones COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here . SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com .

Requirements

Must-haves

Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
Develop, maintain, and optimize physical verification flows for advanced node SoC’s.
Interpret and implement foundry Design Rule Manuals (DRM) — translate rule updates into verified flow changes
Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows
Bachelor’s degree in electrical engineering, computer engineering or computer science
5+ years of ASIC and/or physical design flow development experience in industry
Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.)
Deep expertise in DRC, LVS, PERC and ESD verification methodologies
Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus
Direct foundry DRM experience — able to read, interpret, and implement complex rule decks
Experience at advanced nodes (4nm and below)
Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
Ability to work extended hours and weekends as needed to meet critical project milestones

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipython

Platform: greenhouse
Effort: quick

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)

Parental Leave