Job description

About Samsung Austin Semiconductor Samsung is a world leader in advanced semiconductor technology, founded on the belief that the pursuit of excellence creates a better world. At Samsung Austin Semiconductor, we are Innovating Today to Power the Devices of Tomorrow. Come innovate with us! Position Summary The Chemical Vapor Deposition (CVD) / Thin Films department at the Samsung semiconductor fabrication facility in Taylor, TX is looking for a process engineering manager to head the process engineering sub team. Candidates should be highly motivated, self-directed, technically proficient, and have a strong safety & quality mindset. Role and Responsibilities Here’s What You’ll Be Responsible For: Strategic Leadership & Organizational Alignment: Srategic Translation: Convert high-level site and departmental objectives into a cohesive operational roadmap for Process TRs to execute. Resource Optimization: Manage the allocation of manpower and technical resources across your teams to ensure key deliverables are met. Cross-Functional Synergy: Drive high-level collaboration between Process Engineering, Equipment Engineering, and Process Operations to eliminate bottlenecks and reduce tool downtime. Governance: Establish and maintain standardized protocols for 8D, ALPS, and PCCB processes to ensure consistency across all process pods. Management of Leaders: Leadership Coaching: Mentor Process TRs on how to effectively manage their individual contributors, focusing on goal setting, talent development, and performance management. Performance Architecture: Oversee the annual performance management cycle for the entire process organization, ensuring fair and rigorous evaluation standards are applied by the TRs. Culture Stewardship: Foster a learning-first, high-performance culture across both teams, ensuring that knowledge is shared between the two pods to prevent single-point-of-failure risks. Conflict Resolution: Act as the final escalation point for technical or interpersonal disputes within the process teams. Technical Governance & Risk Management : High-Level Technical Oversight: Provide executive-level guidance on semiconductor processes and integration for 2nm, ensuring technical decisions are sound and sustainable. Risk Mitigation: Oversee the management of abnormalities and deviations; ensure that the TRs are balancing quality guarantees with production and cost objectives. Systems Stewardship: Ensure the optimal utilization of Process systems (eSPEC, PEMS, APC, RMS, YMS) and drive the adoption of new tool-set capabilities. Safety & Compliance: Hold TRs accountable for strict adherence to site-wide safety standards and the achievement of LSM (Loss Safety Management) goals. Operational Excellence & Site Readiness: Mass Production Readiness: Oversee the timeline for new tool process qualification, ensuring that both teams are hitting milestones required for 2nm readiness. CIP Strategy: Drive the overarching Continuous Improvement Process (CIP) for Operations interlocks, holds, and patient lot processes. Executive Communication: Synthesize complex technical data from the TRs into concise reports and presentations for site leadership. Skills and Qualifications Here s what you ll need: Technical Expertise: Deep expertise in 2nm semiconductor process engineering and integration. Leadership Experience: Proven experience managing other managers or leading large, multi-tiered engineering teams in a high-volume manufacturing (HVM) environment. Systems Knowledge: Expert-level understanding of eSPEC, PEMS, APC, RMS, and YMS. Methodology: Mastery of 8D, ALPS, PCCB, TMCB, and RACB process frameworks. Communication: Ability to navigate complex organizational hierarchies and communicate technical risks to non-technical executives. The current base salary range for this role is between $147,000 - $200,500. Individual base pay rates will depend on factors including duties, work location, education, skills, qualifications and experience. Total compensation for this position will include a competitive benefits package and may include participation in company incentive compensation programs, which are based on factors to include organizational and individual performance . Total Rewards At Samsung Austin Semiconductor, base pay is just one part of our total compensation package. The base compensation for this role will depend on education, experience, skills, and location. We offer a comprehensive benefits package, including: Medical, dental, and vision insurance Life insurance and 401(k) matching with immediate vesting Onsite café(s) and workout facilities Paid maternity and paternity leave Paid time off (PTO) 2 personal holidays and 10 regular holidays Wellness incentives and MORE Eligible full-time employees (salaried or hourly) may also receive MBO bonuses based on company, division, and individual performance. All positions at Samsung Austin Semiconductor are full-time on-site. U.S. Export Control This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization. Trade Secrets By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity. * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here . * Samsung Electronics America, Inc. and its subsidiaries are committed to Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Requirements

Must-haves

Role and Responsibilities
Srategic Translation: Convert high-level site and departmental objectives into a cohesive operational roadmap for Process TRs to execute.
Resource Optimization: Manage the allocation of manpower and technical resources across your teams to ensure key deliverables are met.
Cross-Functional Synergy: Drive high-level collaboration between Process Engineering, Equipment Engineering, and Process Operations to eliminate bottlenecks and reduce tool downtime.
Governance: Establish and maintain standardized protocols for 8D, ALPS, and PCCB processes to ensure consistency across all process pods.
Leadership Coaching: Mentor Process TRs on how to effectively manage their individual contributors, focusing on goal setting, talent development, and performance management.
Performance Architecture: Oversee the annual performance management cycle for the entire process organization, ensuring fair and rigorous evaluation standards are applied by the TRs.
Culture Stewardship: Foster a learning-first, high-performance culture across both teams, ensuring that knowledge is shared between the two pods to prevent single-point-of-failure risks.
Conflict Resolution: Act as the final escalation point for technical or interpersonal disputes within the process teams.
High-Level Technical Oversight: Provide executive-level guidance on semiconductor processes and integration for 2nm, ensuring technical decisions are sound and sustainable.
Risk Mitigation: Oversee the management of abnormalities and deviations; ensure that the TRs are balancing quality guarantees with production and cost objectives.
Systems Stewardship: Ensure the optimal utilization of Process systems (eSPEC, PEMS, APC, RMS, YMS) and drive the adoption of new tool-set capabilities.
Safety & Compliance: Hold TRs accountable for strict adherence to site-wide safety standards and the achievement of LSM (Loss Safety Management) goals.
Mass Production Readiness: Oversee the timeline for new tool process qualification, ensuring that both teams are hitting milestones required for 2nm readiness.
CIP Strategy: Drive the overarching Continuous Improvement Process (CIP) for Operations interlocks, holds, and patient lot processes.
Executive Communication: Synthesize complex technical data from the TRs into concise reports and presentations for site leadership.
Skills and Qualifications
Technical Expertise: Deep expertise in 2nm semiconductor process engineering and integration.
Leadership Experience: Proven experience managing other managers or leading large, multi-tiered engineering teams in a high-volume manufacturing (HVM) environment.
Systems Knowledge: Expert-level understanding of eSPEC, PEMS, APC, RMS, and YMS.
Methodology: Mastery of 8D, ALPS, PCCB, TMCB, and RACB process frameworks.
Communication: Ability to navigate complex organizational hierarchies and communicate technical risks to non-technical executives.

Nice-to-haves

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Application prep

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Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)

Pto

Paid Time Off

Wellness