Job description

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are seeking a skilled and driven Silicon Platform Engineer to join the System-on-Chip platform team that works on IP integration, chip-level verification, and firmware development. This is a System-on-Chip design, integration and verification role, working at the intersection of hardware and software. You will shape the platform from IP bring-up through full-chip validation: defining testbenches, authoring test firmware, and implementing critical chip features in silicon. This is a hands-on role with broad impact across the hardware development cycle. Core Responsibilities IP Integration and Verification - IP Integration: Evaluate, integrate, and verify IP blocks within the chip, ensuring correct connectivity, configuration, and interoperability across the platform. - Feature and Module Firmware: Author targeted test firmware to bring up and verify individual IP blocks and hardware features at the module level. - Subsystem Firmware: Develop subsystem-level test firmware to validate interactions between integrated components and confirm correct system behavior across hardware boundaries. Testbench Development and Build Flows - Testbench Infrastructure: Define, implement, and maintain system-level testbenches covering subsystem and full-chip verification scenarios. - Build Flow Management: Own and manage testbench build flows, ensuring reproducibility, scalability, and integration with the broader verification environment. Chip Feature Implementation - Hardware Security: Implement chip-level security features, including secure boot, hardware root of trust, and cryptographic accelerator integration. - Inter-Subsystem Communication: Define and implement communication fabrics and protocols between chip subsystems, including AMBA-based interconnects (AXI, AHB, APB). - Power Management: Implement hardware power management features, including power domain control, clock gating, and low-power state transitions. - Boot Flow and Configuration: Define and implement the chip boot architecture, including reset sequencing, configuration registers, and boot ROM integration. What you bring to this role: Hardware Description Languages: Proficiency in RTL design and verification using SystemVerilog and/or VHDL. Verification Methodologies: Experience with UVM or similar structured verification methodologies. Firmware Development: Ability to write bare-metal C firmware for hardware bring-up, feature validation, and test automation on embedded targets. AMBA Interconnects: Strong knowledge of AMBA protocols (AXI, AHB, APB) and their application in chip integration. Chip Architecture: Understanding of subsystem partitioning, memory maps, interrupt routing, and hardware/software interfaces. Debugging Tools: Experience with simulation tools (e.g., VCS, Questa, Xcelium) and hardware debug environments (JTAG, logic analyzers, oscilloscopes). Scripting: Proficiency in scripting languages such as Python, Tcl, Bash, and Makefiles for build flow automation and test infrastructure. Version Control: Expertise with Git or similar version control systems. Bonus points for the following: - Experience with ARM Corstone reference designs and Cortex-M or Cortex-A processor integration. - Familiarity with TrustedFirmware-M, MCUboot, or PSA-certified security architectures. - Knowledge of embedded security concepts, including cryptographic algorithms and Post-Quantum Cryptography (PQC). - Experience with formal verification or property checking tools. - Familiarity with FPGA emulation platforms for pre-silicon validation. - Knowledge of 3GPP network protocols as they relate to modem or connectivity subsystem integration. - Experience with low-power chip design and power intent methodologies (UPF/CPF). - Familiarity with Cortex-A and Cortex-M class processors, NPU processors, and DSP processors. - Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Collaboration and Documentation: · Cross-Functional Partnership : Work closely with Silicon firmware engineers, RTL designers, and physical design teams to ensure cohesive hardware-software integration throughout the development cycle. · Documentation : Produce and maintain clear technical documentation covering integration specifications, verification plans, test procedures, and feature implementation details. Additional Requirements This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected. This is a full time, exempt position, based out of our Santa Clara office. The target base pay for this position is $150,000 - $220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience. We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that’s your experience – then we’ll be immediately wow-ed. E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role. Why E-Space is right for you: As a member of our team, you will play a crucial role in driving our success. Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals. In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry. We want you to make the most of your journey at E-Space. That’s why we support and invest in the physical, emotional and financial well-being of our team members and their families. Some of what you can expect when working at E-Space: • An opportunity to really make a difference • Sustainability at our core • Fair and honest workplace • Innovative thinking is encouraged • Competitive salaries • Continuous learning and development • Health and wellness care options • Financial solutions for the future • Optional legal services (US only) • Paid holidays • Paid time off

Requirements

Must-haves

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!
IP Integration and Verification
IP Integration: Evaluate, integrate, and verify IP blocks within the chip, ensuring correct connectivity, configuration, and interoperability across the platform.
Feature and Module Firmware: Author targeted test firmware to bring up and verify individual IP blocks and hardware features at the module level.
Subsystem Firmware: Develop subsystem-level test firmware to validate interactions between integrated components and confirm correct system behavior across hardware boundaries.
Testbench Development and Build Flows
Testbench Infrastructure: Define, implement, and maintain system-level testbenches covering subsystem and full-chip verification scenarios.
Build Flow Management: Own and manage testbench build flows, ensuring reproducibility, scalability, and integration with the broader verification environment.
Chip Feature Implementation
Hardware Security: Implement chip-level security features, including secure boot, hardware root of trust, and cryptographic accelerator integration.
Inter-Subsystem Communication: Define and implement communication fabrics and protocols between chip subsystems, including AMBA-based interconnects (AXI, AHB, APB).
Power Management: Implement hardware power management features, including power domain control, clock gating, and low-power state transitions.
Boot Flow and Configuration: Define and implement the chip boot architecture, including reset sequencing, configuration registers, and boot ROM integration.
Hardware Description Languages: Proficiency in RTL design and verification using SystemVerilog and/or VHDL.
Verification Methodologies: Experience with UVM or similar structured verification methodologies.
Firmware Development: Ability to write bare-metal C firmware for hardware bring-up, feature validation, and test automation on embedded targets.
AMBA Interconnects: Strong knowledge of AMBA protocols (AXI, AHB, APB) and their application in chip integration.
Chip Architecture: Understanding of subsystem partitioning, memory maps, interrupt routing, and hardware/software interfaces.
Debugging Tools: Experience with simulation tools (e.g., VCS, Questa, Xcelium) and hardware debug environments (JTAG, logic analyzers, oscilloscopes).
Scripting: Proficiency in scripting languages such as Python, Tcl, Bash, and Makefiles for build flow automation and test infrastructure.
Version Control: Expertise with Git or similar version control systems.
Experience with ARM Corstone reference designs and Cortex-M or Cortex-A processor integration.
Familiarity with TrustedFirmware-M, MCUboot, or PSA-certified security architectures.
Knowledge of embedded security concepts, including cryptographic algorithms and Post-Quantum Cryptography (PQC).

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: lever
Effort: quick

Benefits

Benefits detected in the listing.

Pto

Paid Time Off

Wellness