Job description

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership openai.com with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. SENIOR PRODUCT, TEST AND YIELD ENHANCEMENT ENGINEER — TAIWAN ABOUT THE ROLE Cerebras is seeking a senior VLSI product and test engineer with 10+ years of experience in semiconductor testing, failure analysis and yield enhancement. In this role, you will drive the test strategy for future generations of the Cerebras Wafer Scale Engine in Taiwan. Your work will span AI processors, high-speed I/O and memory; including ATE test development, manufacturing-data analysis, wafer disposition, defect characterization, failure isolation and yield improvement. KEY RESPONSIBILITIES - Develop and optimize production test programs for wafer-scale AI processors. - Drive high-volume manufacturing testing in partnership with foundries and outsourced semiconductor assembly and test providers (OSATs). - Implement and optimize design-for-test strategies, including scan, built-in self-test (BIST), automatic test-pattern generation (ATPG) and functional testing. - Analyze automated test equipment (ATE), Shmoo, parametric and defect data to improve yield and fault tolerance. - Develop failure-analysis and fault-isolation methods for defective cores, tiles and other functional blocks. - Build efficient wafer-level test flows for massively parallel compute, mesh and network-on-chip architectures, and die-to-die interconnects. - Partner closely with DFT, architecture, design, performance, software and manufacturing teams. - Optimize voltage-frequency operating limits, current, thermal behavior, power delivery and parallel die-testing capabilities. - Support wafer and lot disposition decisions throughout high-volume manufacturing. REQUIRED SKILLS AND QUALIFICATIONS - BS or MS in Electrical Engineering, Computer Engineering or a related field. - 10+ years of semiconductor product or test-engineering experience supporting highly integrated devices. - Strong experience in test development, silicon debug, test optimization and yield improvement. - Experience testing large parallel processors, GPUs, CPUs or networking ASICs incorporating SRAM, DDR/DRAM or HBM. - Expert-level, hands-on experience with the Advantest V93000 platform; Teradyne experience is a plus. - Experience specifying, designing, developing and debugging load boards and probe cards for advanced production-test and DFT requirements. - Strong cross-functional collaboration and problem-solving skills. - Experience working with Git-based development and release flows. PREFERRED QUALIFICATIONS - Programming experience with C, C++, Python or Perl for large-scale test-data analysis. - Experience with semiconductor test and failure-analysis tools or techniques such as Tessent, OBIRCH, IREM and LADA. - Experience testing high-speed SerDes at the ATE, package or system level. - Experience with analog blocks embedded within large digital ASICs. - Experience applying advanced data-analysis or machine-learning techniques to yield optimization. - Knowledge of wafer-scale packaging, TSVs, advanced interconnects, in-line diagnostics and defect-mitigation techniques. LOCATION AND TRAVEL This position is based in Taiwan and requires at least 50% travel within Taiwan. Please disregard the mention of the Sunnyvale location, it is listed by default. Why Join Cerebras People who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras: 1. Build a breakthrough AI platform beyond the constraints of the GPU. 2. Publish and open source their cutting-edge AI research. 3. Work on one of the fastest AI supercomputers in the world. 4. Enjoy job stability with startup vitality. 5. Our simple, non-corporate work culture that respects individual beliefs. Find out more about what it's like to work at Cerebras here cerebras.ai! Apply today and become part of the forefront of groundbreaking advancements in AI! Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them. This website or its third-party tools process personal data. For more details, click here cerebras.net to review our CCPA disclosure notice.

Requirements

Must-haves

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
SENIOR PRODUCT, TEST AND YIELD ENHANCEMENT ENGINEER — TAIWAN
Cerebras is seeking a senior VLSI product and test engineer with 10+ years of experience in semiconductor testing, failure analysis and yield enhancement.
Develop and optimize production test programs for wafer-scale AI processors.
Drive high-volume manufacturing testing in partnership with foundries and outsourced semiconductor assembly and test providers (OSATs).
Implement and optimize design-for-test strategies, including scan, built-in self-test (BIST), automatic test-pattern generation (ATPG) and functional testing.
Analyze automated test equipment (ATE), Shmoo, parametric and defect data to improve yield and fault tolerance.
Develop failure-analysis and fault-isolation methods for defective cores, tiles and other functional blocks.
Build efficient wafer-level test flows for massively parallel compute, mesh and network-on-chip architectures, and die-to-die interconnects.
Partner closely with DFT, architecture, design, performance, software and manufacturing teams.
Optimize voltage-frequency operating limits, current, thermal behavior, power delivery and parallel die-testing capabilities.
Support wafer and lot disposition decisions throughout high-volume manufacturing.
BS or MS in Electrical Engineering, Computer Engineering or a related field.
10+ years of semiconductor product or test-engineering experience supporting highly integrated devices.
Strong experience in test development, silicon debug, test optimization and yield improvement.
Experience testing large parallel processors, GPUs, CPUs or networking ASICs incorporating SRAM, DDR/DRAM or HBM.
Experience specifying, designing, developing and debugging load boards and probe cards for advanced production-test and DFT requirements.

Nice-to-haves

Expert-level, hands-on experience with the Advantest V93000 platform; Teradyne experience is a plus.
Programming experience with C, C++, Python or Perl for large-scale test-data analysis.
Experience with semiconductor test and failure-analysis tools or techniques such as Tessent, OBIRCH, IREM and LADA.
Experience testing high-speed SerDes at the ATE, package or system level.
Experience with analog blocks embedded within large digital ASICs.
Experience applying advanced data-analysis or machine-learning techniques to yield optimization.
Knowledge of wafer-scale packaging, TSVs, advanced interconnects, in-line diagnostics and defect-mitigation techniques.

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