Job description

About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is building a new category of AI hardware: frontier inference clusters. As a top-level PD engineer, you will own full-chip implementation—encompassing floorplanning, P&R, clocking, timing analysis, physical verification, and sign-offs—from synthesis through to GDSII completion. You will lead critical efforts in these areas, leveraging our PD flows to drive aggressive PPA optimization and timing closure. You will collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market. Key Responsibilities - Own full-chip clocking across all PVT corners and modes. - Manage MMMC (Multi-Mode Multi-Corner) timing closure at the top level. - Own timing constraints and hierarchical timing budgeting between top level and blocks. - Drive functional and timing ECO closure and achieve final timing signoff for tapeout. - Own end-to-end physical verification closure at block, sub-system, and full-chip level across DRC, LVS, ERC, antenna, density, fill, and top-level integration. - Debug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool or setup issues, and fix violations directly in layout using Innovus. - Build a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews. You may be a good fit if you have - 10+ years of previous experience with chip planning, top level PD, floorplanning - Experience with top-level and full-chip closure on advanced process nodes (5nm and below) - Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows - Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff - Experience with Pegasus or Calibre for physical verification signoff - Experience with hierarchical timing budgeting, constraint management, and ECO closure - Experience with Cadence Innovus for top-level assembly, routing, and layout fixes - Deeply creative and able to think from first principles Strong candidates may also have experience with - Familiarity with modern ML and LLM model architectures - Ability to program with Python or another scripting language - Familiarity with AI tools for programming/coding - Startup experience or comfort working in fast-paced environments Benefits - Medical, dental, and vision packages with generous premium coverage - $500 per month credit for waiving medical benefits - Housing subsidy of $2.5k per month for those living within walking distance of the office - Relocation support for those moving to San Jose (Santana Row) - Various wellness benefits covering fitness, mental health, and more - Daily lunch and dinner in our office - Unlimited compute budget subject to ROI justification How we’re different Etched believes in the Bitter Lesson incompleteideas.net. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

Requirements

Must-haves

Own full-chip clocking across all PVT corners and modes.
Manage MMMC (Multi-Mode Multi-Corner) timing closure at the top level.
Own timing constraints and hierarchical timing budgeting between top level and blocks.
Drive functional and timing ECO closure and achieve final timing signoff for tapeout.
Own end-to-end physical verification closure at block, sub-system, and full-chip level across DRC, LVS, ERC, antenna, density, fill, and top-level integration.
Debug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool or setup issues, and fix violations directly in layout using Innovus.
Build a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews.
You may be a good fit if you have
10+ years of previous experience with chip planning, top level PD, floorplanning
Experience with top-level and full-chip closure on advanced process nodes (5nm and below)
Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff
Experience with Pegasus or Calibre for physical verification signoff
Experience with hierarchical timing budgeting, constraint management, and ECO closure
Experience with Cadence Innovus for top-level assembly, routing, and layout fixes
Deeply creative and able to think from first principles
Strong candidates may also have experience with
Familiarity with modern ML and LLM model architectures
Ability to program with Python or another scripting language
Familiarity with AI tools for programming/coding
Startup experience or comfort working in fast-paced environments

Nice-to-haves

None flagged.

Application prep

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Keywords to mirror

aimlllmpython

Platform: ashby
Effort: quick

Benefits

Benefits detected in the listing.

Dental

Vision

Wellness