Job description

About Tensordyne Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Tensordyne is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment. About the role: As a member of Tensordyne’s ASIC team, you will be responsible for the microarchitecture and design implementation of high-performance AI ASICs. These ASICs closely couple novel computational accelerator units, compute, interconnects, networking and 3rd-party IP blocks as needed to redefine the next generation of tokenomics for inference. Your responsibilities will be wide-ranging and span at minimum the following: Responsibilities: Work with architecture on reconciling changes with respect to micro-architecture Define microarchitecture and document Select and integrate 3rd-party IP blocks Collaborate with design verification engineers Run, analyse frontend synthesis and address all issues Collaborate with backend teams on place-and-route guidance and timing closure Ability to leverage GenAI usage across all workflows, while retaining ownership and quality of all generated collateral Required Qualifications: 3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog. Experience in IP integration, specifically CPU IP into SoC. Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation Familiarity with AMBA/APB/AXI Protocol Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C .... Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies. Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains Previous experience with timing closure at high frequencies is a plus. Interest to explore AI architectures for convolution, transformer and other kinds of workloads Self-starter and highly-motivated to work in a dynamic start-up environment. B.S. (M.S. preferred) degree in Electrical or Computer engineering. Tensordyne's culture was built on the following values that are equally important to us as business: Put people first. We only succeed when our people succeed. Ethics and integrity always; Being open, honest, and respectful of everyone. Think Big. Be ambitious and have audacious goals. Aim for excellence. Quality and excellence count in everything we do. Own it and get it done. Results matter! Make Each Person Better together than they would be as an individual. Embrace each others’ differences. Embrace that there will be differences. Tensordyne is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.

Requirements

Must-haves

Your responsibilities will be wide-ranging and span at minimum the following:
Work with architecture on reconciling changes with respect to micro-architecture
Define microarchitecture and document
Select and integrate 3rd-party IP blocks
Collaborate with design verification engineers
Run, analyse frontend synthesis and address all issues
Collaborate with backend teams on place-and-route guidance and timing closure
Ability to leverage GenAI usage across all workflows, while retaining ownership and quality of all generated collateral
3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.
Experience in IP integration, specifically CPU IP into SoC.
Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
Familiarity with AMBA/APB/AXI Protocol
Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ....
Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies.
Familiarity with low power design. UPF flow for defining power intent of chips with multiple power domains
Interest to explore AI architectures for convolution, transformer and other kinds of workloads
Self-starter and highly-motivated to work in a dynamic start-up environment.
Tensordyne's culture was built on the following values that are equally important to us as business:
Put people first. We only succeed when our people succeed.
Ethics and integrity always; Being open, honest, and respectful of everyone.
Think Big. Be ambitious and have audacious goals.
Aim for excellence. Quality and excellence count in everything we do.

Nice-to-haves

Previous experience with timing closure at high frequencies is a plus.
B.S. (M.S. preferred) degree in Electrical or Computer engineering.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

Platform: greenhouse
Effort: quick