Job description

Location: Ottawa, ON (on-site) Employment type: Full-time permanent Salary range: $105,000 – $145,000 CAD per year About Q-Block Computing: Q-Block Computing builds quantum systems that operate in the real world. The company develops quantum timing, quantum-secure communications, and quantum computing platforms engineered for the performance, reliability, and environmental resilience that mission-critical applications demand — systems designed to be deployed, maintained, and trusted by operators who cannot afford ambiguity about whether the technology works. The long-term vision is deeper than any single platform. Q-Block is pursuing a mission to decode Nature's foundational model — to build instruments of sufficient precision and coherence that they become tools for understanding the physical universe at its most fundamental level. Commercialization and science reinforce each other by design. About this role: The FPGA Engineer designs and implements the real-time processing and control logic that sits closest to Q-Block's quantum hardware — the fabric that acquires, synchronizes, and acts on signals at speeds and determinism the software stack alone cannot reach. The work spans RTL design and verification, high-speed ADC/DAC and serial interfaces, real-time DSP pipelines, and sub-microsecond timing and synchronization across multi-channel and multi-node systems. The successful candidate is an RTL engineer who is fluent in both design and verification, comfortable carrying a module from specification through simulation, timing closure, and on-hardware debug. They read datasheets as reference material, treat clock domain crossings and metastability with the seriousness they deserve, and enjoy the moment when a pipeline finally meets timing and the scope shows exactly what the spec predicted. The role reports into the Technical Lead — Orchestration Control and works across firmware, hardware, platform, and scientific teams. Responsibilities • Design, implement, simulate, and verify RTL modules in VHDL or Verilog for FPGA-based real-time control and data acquisition subsystems. • Develop high-speed digital interfaces between FPGA fabric and external peripherals, including ADCs, DACs, DDS synthesizers, and high-speed serial transceivers. • Implement real-time signal processing pipelines within FPGA fabric, including filtering, decimation, accumulation, and feedback control paths. • Design and implement deterministic timing and synchronization logic to coordinate multi-channel and multi-node hardware operations at sub-microsecond precision. • Develop and maintain FPGA build flows, constraint files, and synthesis scripts for target platforms. • Create simulation testbenches and verification environments to validate RTL functionality, timing closure, and interface compliance prior to hardware deployment. • Integrate FPGA subsystems with embedded firmware running on ARM Cortex-M or similar microcontrollers via shared-memory, SPI, AXI, or comparable interfaces. • Perform on-hardware debugging and characterization using logic analyzers, oscilloscopes, and embedded instrumentation (ILA, SignalTap). • Write and maintain documentation for FPGA architectures, interface protocols, register maps, and test procedures. • Participate in design reviews and contribute to the engineering standards of the team. • Collaborate across firmware, hardware, infrastructure, and systems teams to translate system-level requirements into robust FPGA deliverables. • Contribute to a culture of continuous learning, rigorous engineering practice, and honest technical discussion. Required qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, Engineering Physics, Physics, or a closely related field; Master's degree is an asset. • 4+ years of professional experience in FPGA design and verification using VHDL, Verilog, or SystemVerilog. • Strong proficiency in RTL design with demonstrated ownership of modules from specification through synthesis and timing closure. • Hands-on experience with Xilinx Vivado, Intel Quartus, or Lattice toolchains, including timing constraint definition and closure. • Solid understanding of high-speed digital design principles: clock domain crossings, pipelining, resource utilization optimization, and metastability mitigation. • Hands-on proficiency with laboratory instruments such as oscilloscopes, logic analyzers, and signal generators. Preferred qualifications • Experience implementing high-speed ADC/DAC interfaces, JESD204B/C, LVDS, or multi-gigabit serial transceivers on FPGA. • Experience with digital signal processing implementation in FPGA fabric (FIR/IIR filters, NCOs, CORDICs, polyphase structures, channelizers). • Experience with Xilinx Zynq, Zynq UltraScale+, or comparable SoC-FPGA platforms, including AXI-based integration and soft-core processors. • Experience with deterministic, low-latency feedback control loops implemented in FPGA fabric. • Experience with multi-FPGA synchronization, distributed clocking, and board-to-board timing distribution. • Experience with advanced verification methodologies (UVM, cocotb, formal verification, or comparable). • Familiarity with scripting and automation for FPGA flows (Tcl, Python) and CI practices applied to RTL. • Experience in scientific, defense, or deep-tech hardware environments — photonics, RF, quantum, radar, aerospace, or precision measurement. Security and compliance requirements • Must be eligible to obtain and maintain Government of Canada security clearance, if required for assigned projects. • Must be eligible to comply with requirements of the Controlled Goods Program, if required for assigned projects. • Must be willing to participate in background screening, documentation, and compliance processes associated with security-sensitive work. • Experience working in regulated, security-sensitive, or defense-oriented engineering environments is an asset. Skills and attributes • Strong attention to detail, authenticity, and a sense of responsibility in all tasks. • Critical thinking and a problem-solving mindset grounded in measurement and evidence. • Clear written and verbal communication; ability to produce RTL documentation and verification reports that hold up under rigorous review. • Strong interpersonal skills and the ability to work collaboratively in a dynamic, multidisciplinary team. Benefits • Extended health care (including dental and vision) • Life insurance Equal opportunity Q-Block Computing is an equal opportunity employer. We are committed to treating all employees and applicants with respect and dignity. Accommodations are available on request during the application and recruiting process. Canadian citizens and permanent residents are strongly encouraged to apply. All interested candidates are encouraged to apply.

Requirements

Must-haves

Location: Ottawa, ON (on-site)
Employment type: Full-time permanent
Design, implement, simulate, and verify RTL modules in VHDL or Verilog for FPGA-based real-time control and data acquisition subsystems.
Develop high-speed digital interfaces between FPGA fabric and external peripherals, including ADCs, DACs, DDS synthesizers, and high-speed serial transceivers.
Implement real-time signal processing pipelines within FPGA fabric, including filtering, decimation, accumulation, and feedback control paths.
Design and implement deterministic timing and synchronization logic to coordinate multi-channel and multi-node hardware operations at sub-microsecond precision.
Develop and maintain FPGA build flows, constraint files, and synthesis scripts for target platforms.
Create simulation testbenches and verification environments to validate RTL functionality, timing closure, and interface compliance prior to hardware deployment.
Integrate FPGA subsystems with embedded firmware running on ARM Cortex-M or similar microcontrollers via shared-memory, SPI, AXI, or comparable interfaces.
Perform on-hardware debugging and characterization using logic analyzers, oscilloscopes, and embedded instrumentation (ILA, SignalTap).
Write and maintain documentation for FPGA architectures, interface protocols, register maps, and test procedures.
Participate in design reviews and contribute to the engineering standards of the team.

Nice-to-haves

Experience implementing high-speed ADC/DAC interfaces, JESD204B/C, LVDS, or multi-gigabit serial transceivers on FPGA.
Experience with digital signal processing implementation in FPGA fabric (FIR/IIR filters, NCOs, CORDICs, polyphase structures, channelizers).
Experience with Xilinx Zynq, Zynq UltraScale+, or comparable SoC-FPGA platforms, including AXI-based integration and soft-core processors.
Experience with deterministic, low-latency feedback control loops implemented in FPGA fabric.
Experience with multi-FPGA synchronization, distributed clocking, and board-to-board timing distribution.
Experience with advanced verification methodologies (UVM, cocotb, formal verification, or comparable).
Familiarity with scripting and automation for FPGA flows (Tcl, Python) and CI practices applied to RTL.
Experience in scientific, defense, or deep-tech hardware environments — photonics, RF, quantum, radar, aerospace, or precision measurement.
Security and compliance requirements
Must be willing to participate in background screening, documentation, and compliance processes associated with security-sensitive work.
Experience working in regulated, security-sensitive, or defense-oriented engineering environments is an asset.
Skills and attributes

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: breezy
Effort: medium

Benefits

Benefits detected in the listing.

Dental

Vision