Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE: We are seeking a lead PPA Architect to ensure that CPU Core & Cache complexes used in embedded products meets the product performance requirements while operating within reliability and system platform constraints. This is a technical leadership role ensuring interlock between CPU IP definition from the Cores design team and the Embedded BU’s unique per-product usage model and operating conditions, and the package & platform impact to the power delivery network and thermal management. THE PERSON: You will be a proven technical leader with the ability to drive cross-functional alignment and execution across architecture, physical design implementation, FW/BIOS, SIPI, and platform teams, ensuring timely closure and multi-dimensional alignment of reliability, power delivery, thermal management and performance constraints. You will also be highly organized and execution-driven, with demonstrated success owning end-to-end technical workstreams and driving closure of open issues, risks, and dependencies across program milestones. KEY RESPONSIBILITIES: Align Product Requirements with Cores IP • Drive alignment on usage model (Product Lifetime, % residency in different CPU operating states, etc.), and operating condition constraints (Min/max ambient/case temp, TDC/EDC, customer-specific failure rate specs, etc.) as it impact achievable performance at power. • Drive alignment on power delivery architecture, packaging infrastructure, and platform definition as it impacts assumed power delivery margins and define new margin requirements. • Drive alignment on thermal modeling, packaging & platform definition as it impact assumed thermal operating margins and define new margin requirements. • Translate product usage model, workload, and reliability requirements into IP performance, power, and thermal constraints. • Drive alignment between Embedded BU product roadmap and available CPU IPs, providing critical technical feedback to Embedded product teams and CPU design teams. • Drive alignment and lead technical reviews across the product definition stack: SoC architecture, physical design implementation, package design and platform definition. Bounding Box / Targets / Program Readiness • Drive power targets and bounding box (BBox) readiness inputs for program reviews, including data-backed tradeoffs (power vs perf vs platform cost/simplicity). • Own a structured “open items” closure mechanism for performance and power topics (risks, dependencies, decisions needed) and represent the workstream in cross‑functional program forums. Tight Partnership with Cores Power & Performance Modeling • Partner closely with the power & performance modeling team to align assumptions, rail targets, use-case definitions, and power feature behaviors that affect model outputs and architectural decisions. • Consume model outputs to drive architecture decisions (budgets, targets, BBox), and provide clear, traceable inputs/constraints back into the modeling loop. Tight Partnership with Cores Advanced Methodology team • Partner closely with Cores power delivery, thermals, and reliability technical leads to ensure the highly aggressive operating targets are met while simultaneously delivering high performance CPU products. • Provide critical feedback to Embedded BU in these technical areas around SoC, package, and platform design to ensure reliable and robust operation. KEY RESPONSIBILITIES • Strong understanding of SoC architecture and design fundamentals: rails, low power modes, performance states, power targets/use cases, platform and system driven constraints. • Working knowledge of PDN and PI principles (IR drop, droop, impedance, decaps, noise budgeting) and ability to drive closure with SIPI/packaging/platform partners. • Working knowledge of device and system reliability requirements, and thermal management algorithms. • Demonstrated ability to lead complex cross‑functional execution (architecture ↔ FW/BIOS ↔ validation ↔ package/platform). • Familiarity collaborating with pre‑silicon power & performance modeling teams and aligning architecture assumptions/targets with projections. • Experience with program milestone readiness (bringing a technical workstream to a “review‑ready” state). ACADEMIC CREDENTIALS • BS/MS in EE/CE (or equivalent) with 7-10 years of relevant experience. LOCATION: Santa Clara, CA #LI-SL2 Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Requirements

Must-haves

ADVANCE YOUR CAREER. ADVANCE THE WORLD.
Align Product Requirements with Cores IP
Drive alignment on power delivery architecture, packaging infrastructure, and platform definition as it impacts assumed power delivery margins and define new margin requirements.
Drive alignment on thermal modeling, packaging & platform definition as it impact assumed thermal operating margins and define new margin requirements.
Translate product usage model, workload, and reliability requirements into IP performance, power, and thermal constraints.
Drive alignment between Embedded BU product roadmap and available CPU IPs, providing critical technical feedback to Embedded product teams and CPU design teams.
Drive alignment and lead technical reviews across the product definition stack: SoC architecture, physical design implementation, package design and platform definition.
Bounding Box / Targets / Program Readiness
Drive power targets and bounding box (BBox) readiness inputs for program reviews, including data-backed tradeoffs (power vs perf vs platform cost/simplicity).
Own a structured “open items” closure mechanism for performance and power topics (risks, dependencies, decisions needed) and represent the workstream in cross‑functional program forums.
Tight Partnership with Cores Power & Performance Modeling
Partner closely with the power & performance modeling team to align assumptions, rail targets, use-case definitions, and power feature behaviors that affect model outputs and architectural decisions.
Consume model outputs to drive architecture decisions (budgets, targets, BBox), and provide clear, traceable inputs/constraints back into the modeling loop.
Tight Partnership with Cores Advanced Methodology team
Partner closely with Cores power delivery, thermals, and reliability technical leads to ensure the highly aggressive operating targets are met while simultaneously delivering high performance CPU products.
Provide critical feedback to Embedded BU in these technical areas around SoC, package, and platform design to ensure reliable and robust operation.
Strong understanding of SoC architecture and design fundamentals: rails, low power modes, performance states, power targets/use cases, platform and system driven constraints.
Working knowledge of PDN and PI principles (IR drop, droop, impedance, decaps, noise budgeting) and ability to drive closure with SIPI/packaging/platform partners.
Working knowledge of device and system reliability requirements, and thermal management algorithms.
Demonstrated ability to lead complex cross‑functional execution (architecture ↔ FW/BIOS ↔ validation ↔ package/platform).
Familiarity collaborating with pre‑silicon power & performance modeling teams and aligning architecture assumptions/targets with projections.
Experience with program milestone readiness (bringing a technical workstream to a “review‑ready” state).
BS/MS in EE/CE (or equivalent) with 7-10 years of relevant experience.
Santa Clara, CA

Nice-to-haves

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Application prep

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Keywords to mirror

aigo

Platform: amd
Effort: medium