Job description

Application close date: 02/12/2027 At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!  - We are collaborators, doers, and problem-solvers who are relentlessly committed to a culture of safety. This position will directly impact the history of space exploration and will require your commitment and detailed attention towards safe and repeatable space flight. Join us in lowering the cost of access to space and enabling Blue Origin’s vision of millions of people living and working in space to benefit Earth. Multiple positions available across our Business Units. You will be matched with an appropriate engineering team based on your skillset and experience and our current business needs. Timeline: Applications will be reviewed on a rolling basis. Primary locations: We prioritize placing early career engineers in locations where they can be co-located with their team and the relevant hardware they support. Please indicate in the application where you would be willing to be located. Responsibilities include but are not limited to:   Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs Support module-level and subsystem-level verification using SystemVerilog/UVM Write test plans and functional coverage definitions under guidance from senior team members Assist with CDC/RDC/LINT checks and clean-up Participate in code coverage and functional coverage closure activities Help develop assertions, protocol monitors, and scoreboards for testbenches Support integration and verification of external IP (e.g., bus fabrics, standard interfaces) Learn and apply industry-standard verification methodologies (UVM, formal verification basics) Debug RTL and testbench issues with guidance from senior engineers Document design intent, verification results, and test coverage Qualifications: BS or MS in Electrical Engineering, Computer Engineering, or related technical field (completed or in final year) Coursework or project experience with Verilog/SystemVerilog RTL design or verification Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing) Familiarity with basic verification concepts (testbenches, simulation, coverage) Strong problem-solving skills and attention to detail Effective communication and ability to work in a collaborative team environment Desired: Academic or internship experience with SystemVerilog/UVM Exposure to scripting languages (Python, Perl, Tcl) for automation/tooling Coursework or projects involving communications systems, DSP, or FPGA design Familiarity with common EDA tools (e.g., VCS, Xcelium, Questa, formal tools) Understanding of computer architecture fundamentals (CPUs, bus protocols like AXI) Personal projects, capstone work, or research involving digital design/verification (e.g., GitHub repos, senior design projects) Base Pay Range for: CA applicants is $129,032.00 - $180,644.10 WA applicants is $129,032.00 - $180,644.10 Other site ranges may differ Culture Statement Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles. Export Control Regulations Applicants for employment at Blue Origin must be a U.S. citizen or national, U.S. permanent resident (i.e. current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Background Check Required for all positions: Blue’s Standard Background Check Required for Certain Job Profiles: Defense Biometric Identification System (DBIDS) background check if at any time the role requires one to be on a military installation Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs. and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing, vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for certain Job Profiles: Ability to obtain and maintain Merchant Mariner Credential, which includes pre-employment and random drug testing as well as DOT physical Benefits Benefits include: Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program. Stock Options for all regular employees (working at least 20 hours/week) Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays. Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company s intent to reward individual contributions and enable them to share in the company s results, or other factors at the company s sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details. Equal Employment Opportunity Blue Origin is proud to be an Equal Opportunity/Affirmative Action Employer and is committed to attracting, retaining, and developing a highly qualified and dedicated work force. Blue Origin hires and promotes people on the basis of their qualifications, performance, and abilities. We support the establishment and maintenance of a workplace that fosters trust, equality, and teamwork. We provide all qualified applicants for employment and employees with equal opportunities for hire, promotion, and other terms and conditions of employment, regardless of their race, color, religion, sex, sexual orientation, gender identity, national origin/ethnicity, age, physical or mental disability, genetic factors, military/veteran status, or any other status or characteristic protected by federal, state, and/or local law. Blue Origin will consider for employment qualified applicants with criminal histories in a manner consistent with applicable federal, state, and local laws, including the Washington Fair Chance Act, the California Fair Chance Act, the Los Angeles Fair Chance in Hiring Ordinance, and other applicable laws. For more information on “Know Your Rights,” please see here . Affirmative Action and Disability Accommodation Applicants wishing to receive information on Blue Origin’s Affirmative Action Plans, or applicants requiring a reasonable accommodation in order to participate in the application and/or interview process, please contact us at EEOCompliance blueorigin.com . Please note this is a publicly managed inbox. Please do not include any personal medical information in your request.

Requirements

Must-haves

Multiple positions available across our Business Units. You will be matched with an appropriate engineering team based on your skillset and experience and our current business needs.
Timeline: Applications will be reviewed on a rolling basis.
We prioritize placing early career engineers in locations where they can be co-located with their team and the relevant hardware they support. Please indicate in the application where you would be willing to be located.
Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs
Support module-level and subsystem-level verification using SystemVerilog/UVM
Write test plans and functional coverage definitions under guidance from senior team members
Assist with CDC/RDC/LINT checks and clean-up
Participate in code coverage and functional coverage closure activities
Help develop assertions, protocol monitors, and scoreboards for testbenches
Support integration and verification of external IP (e.g., bus fabrics, standard interfaces)
Learn and apply industry-standard verification methodologies (UVM, formal verification basics)
Debug RTL and testbench issues with guidance from senior engineers
Document design intent, verification results, and test coverage
BS or MS in Electrical Engineering, Computer Engineering, or related technical field (completed or in final year)
Coursework or project experience with Verilog/SystemVerilog RTL design or verification
Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing)
Familiarity with basic verification concepts (testbenches, simulation, coverage)
Strong problem-solving skills and attention to detail

Nice-to-haves

Academic or internship experience with SystemVerilog/UVM
Exposure to scripting languages (Python, Perl, Tcl) for automation/tooling
Coursework or projects involving communications systems, DSP, or FPGA design
Familiarity with common EDA tools (e.g., VCS, Xcelium, Questa, formal tools)
Understanding of computer architecture fundamentals (CPUs, bus protocols like AXI)
Personal projects, capstone work, or research involving digital design/verification (e.g., GitHub repos, senior design projects)

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)

Paid Time Off

Parental Leave