Job description

Duration: 12+ Months Job Description: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: • RTL design for memory I/O • PHY Digital Architecture development from pathfinding, coding, verification to physical implementation PHY link layer design, implementation & verification with Analog and System architect. • PHY Analog/Digital co-design • Digital design and RTL coding • Timing Synthesis & Drive Physical implementation Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Estimate the time required to write the new feature tests and any required changes to the test environment Build the unit tests Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues Experience: • Digital design engineering experience • Experienced with Verilog, System Verilog, C, and C++ Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus Knowledge of clocking architectures, synchronization, and CDC methodology Experience with synthesis, Timing closure SERDES, DDR, Memory Controller, or MAC Design experience is preferred Proficient in debugging firmware and RTL code using simulation tools Strong understanding of computer organization/architecture. • Mixed signal RTL, Low power design experience is a plus Exposure to leadership or mentorship is an asset About US Tech Solutions: US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com . US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. AI Statement : By applying, you acknowledge that AI-assisted tools may be used during hiring.

Requirements

Must-haves

Duration: 12+ Months
RTL design for memory I/O
PHY Digital Architecture development from pathfinding, coding, verification to physical implementation PHY link layer design, implementation & verification with Analog and System architect.
PHY Analog/Digital co-design
Digital design and RTL coding
Digital design engineering experience

Nice-to-haves

Mixed signal RTL, Low power design experience is a plus Exposure to leadership or mentorship is an asset

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

pythonai

Platform: jobdiva
Effort: medium