Job description

Director, ASIC Design & Front-End Implementation This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Lead the ASIC Design and Front-End Implementation organization responsible for delivering next-generation networking ASICs that power HPE Networking products and technology roadmaps. Drive RTL design execution, implementation readiness, design quality, and milestone delivery from architecture through tapeout, silicon bring-up, and product deployment. Partner closely with Architecture, Verification, Emulation, Software/SDK, Physical Design, Post-Silicon Engineering, Product Management, and Product Marketing to ensure successful execution and alignment with business objectives. ASIC Design Leadership Lead RTL design and microarchitecture teams developing complex networking ASICs. Drive design execution from architecture through RTL completion, ensuring performance, power, area (PPA), quality, cost, and schedule targets are met. Establish design methodologies, coding standards, and engineering best practices. Review and approve key architectural and implementation trade-offs. Implementation & Tapeout Readiness Partner with Physical Design teams to achieve floorplanning, timing closure, power optimization, DFT integration, and tapeout readiness. Ensure RTL designs are optimized for implementation, manufacturability, scalability, and production readiness. Support issue resolution through implementation, silicon validation, and bring-up. Cross-Functional Leadership Collaborate across Architecture, Verification, Emulation, SDK/Software, Physical Design, Post-Silicon Engineering, Product Management, and Product Marketing. Align product requirements, architecture, RTL implementation, verification, software enablement, and deployment plans. Lead design reviews, milestone assessments, technical risk evaluations, and issue resolution. Technology & Product Strategy Contribute to ASIC technology strategy and product roadmaps through technical feasibility, cost, performance, and schedule analysis. Collaborate with Architecture and Product teams to define future networking ASIC capabilities and competitive differentiation. Represent the design organization in roadmap reviews, executive discussions, and customer engagements. Program & People Leadership Drive execution across multiple ASIC programs, managing schedules, dependencies, risks, and deliverables. Lead engineering managers and senior technical contributors while recruiting, developing, and retaining top talent. Foster a culture of accountability, technical excellence, innovation, and continuous learning. Methodology & Productivity Improve design quality, engineering productivity, and execution efficiency through automation, CI/CD, and modern development practices. Champion AI-assisted engineering tools and methodology enhancements that improve predictability, quality, and time-to-market. Qualifications Required BS/MS in Electrical Engineering, Computer Engineering, or related field. 15 years of ASIC development experience, including 8 years leading engineering teams and managers. Expertise in RTL design, Verilog/SystemVerilog, microarchitecture development, synthesis, CDC, linting, timing closure, and ASIC implementation flows. Proven success delivering complex ASICs from concept through production. Strong cross-functional (Architecture, Verification, Physical Design, Software, Emulation, and Post-Silicon) leadership, communication, and program execution skills. Preferred Experience with networking ASICs, switching/routing architectures, packet processing, QoS, security, telemetry, and AI networking solutions. Experience in silicon bring-up, validation, and post-silicon debug. Background collaborating with Product Management and Marketing on roadmap planning. Experience leading globally distributed engineering organizations. Track record of driving methodology, automation, and productivity improvements, including AI-assisted engineering workflows. What We Can Offer You: Health & Wellbeing We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing. Personal & Professional Development We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division. Unconditional Inclusion We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. Let s Stay Connected: Follow HPECareers on Instagram to see the latest on people, culture and tech at HPE. Job: Engineering Job Level: Director Information about employee benefits offered in the US can be found at myhperewards.com HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity . Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities. HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories. Recruitment Fraud Alert We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications. All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.

Requirements

Must-haves

Director, ASIC Design & Front-End Implementation
ASIC Design Leadership
Lead RTL design and microarchitecture teams developing complex networking ASICs.
Drive design execution from architecture through RTL completion, ensuring performance, power, area (PPA), quality, cost, and schedule targets are met.
Establish design methodologies, coding standards, and engineering best practices.
Review and approve key architectural and implementation trade-offs.
Implementation & Tapeout Readiness
Partner with Physical Design teams to achieve floorplanning, timing closure, power optimization, DFT integration, and tapeout readiness.
Ensure RTL designs are optimized for implementation, manufacturability, scalability, and production readiness.
Support issue resolution through implementation, silicon validation, and bring-up.
Cross-Functional Leadership
Collaborate across Architecture, Verification, Emulation, SDK/Software, Physical Design, Post-Silicon Engineering, Product Management, and Product Marketing.
Align product requirements, architecture, RTL implementation, verification, software enablement, and deployment plans.
Lead design reviews, milestone assessments, technical risk evaluations, and issue resolution.
Technology & Product Strategy
Contribute to ASIC technology strategy and product roadmaps through technical feasibility, cost, performance, and schedule analysis.
Collaborate with Architecture and Product teams to define future networking ASIC capabilities and competitive differentiation.
Represent the design organization in roadmap reviews, executive discussions, and customer engagements.
Program & People Leadership

Nice-to-haves

Experience with networking ASICs, switching/routing architectures, packet processing, QoS, security, telemetry, and AI networking solutions.
Experience in silicon bring-up, validation, and post-silicon debug.
Background collaborating with Product Management and Marketing on roadmap planning.
Experience leading globally distributed engineering organizations.
Track record of driving methodology, automation, and productivity improvements, including AI-assisted engineering workflows.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

ci/cdai

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Vision

Professional Development