Job description

As a Silicon Power and Performance Architect for Pixel AR/VR, you will drive the engaged and architectural analysis that defines the future of Google's consumer hardware. AR and VR use cases demand immersive, zero-latency experiences under incredibly tight thermal and power constraints. You will analyze how spatial computing workloads impact the broader Pixel system-on-chip (SoC) power envelope, identifying bottlenecks, evaluating competitor architectures, and proposing silicon-level optimizations to ensure Pixel remains a market leader. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google . • Benchmark and model next-generation AR/VR use cases against industry competitors to identify architectural gaps and opportunities. • Analyze end-to-end workloads (spatial mapping, hand tracking, passthrough video) to quantify their impact on total Pixel power consumption. • Leverage low-power design techniques, specifically optimizing the utilization of low-power islands (LPIs) to keep ambient AR/VR tasks highly efficient. • Map and optimize critical data paths from the display/sensors through the SoC fabric and the path to DDR, ensuring maximum bandwidth with minimal power overhead. • Partner with software, product, and hardware teams to translate architectural insights into actionable silicon requirements for future Pixel SoCs. • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience. • 4 years of experience in SoC architecture, power/performance modeling, or pre-silicon verification. • Experience with low-power design methodologies or power management techniques (e.g., power gating, DVFS, low-power states). • Experience with memory subsystems, interconnects, or data paths to DDR. Minimum qualifications: • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience. • 4 years of experience in SoC architecture, power/performance modeling, or pre-silicon verification. • Experience with low-power design methodologies or power management techniques (e.g., power gating, DVFS, low-power states). • Experience with memory subsystems, interconnects, or data paths to DDR. Preferred qualifications: • Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP). • Experience specifically analyzing or architecting mobile/wearable SoCs for AR, VR, or computer vision applications. • Experience with architectural simulators or power estimation tools (e.g., Synopsys PrimePower, ANSYS PowerArtist, or proprietary modeling frameworks). • Practical knowledge of low-power islands (LPI) or always-on subsystem architectures. • Excellent communication skills to translate complex architectural trade-offs into clear product decisions for leadership.

Requirements

Must-haves

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
Learn more about benefits at Google .
Benchmark and model next-generation AR/VR use cases against industry competitors to identify architectural gaps and opportunities.
Analyze end-to-end workloads (spatial mapping, hand tracking, passthrough video) to quantify their impact on total Pixel power consumption.
Leverage low-power design techniques, specifically optimizing the utilization of low-power islands (LPIs) to keep ambient AR/VR tasks highly efficient.
Map and optimize critical data paths from the display/sensors through the SoC fabric and the path to DDR, ensuring maximum bandwidth with minimal power overhead.
Partner with software, product, and hardware teams to translate architectural insights into actionable silicon requirements for future Pixel SoCs.
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
4 years of experience in SoC architecture, power/performance modeling, or pre-silicon verification.
Experience with low-power design methodologies or power management techniques (e.g., power gating, DVFS, low-power states).
Experience with memory subsystems, interconnects, or data paths to DDR.
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
4 years of experience in SoC architecture, power/performance modeling, or pre-silicon verification.
Experience with low-power design methodologies or power management techniques (e.g., power gating, DVFS, low-power states).
Experience with memory subsystems, interconnects, or data paths to DDR.

Nice-to-haves

US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits
Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP).
Experience specifically analyzing or architecting mobile/wearable SoCs for AR, VR, or computer vision applications.
Experience with architectural simulators or power estimation tools (e.g., Synopsys PrimePower, ANSYS PowerArtist, or proprietary modeling frameworks).
Practical knowledge of low-power islands (LPI) or always-on subsystem architectures.
Excellent communication skills to translate complex architectural trade-offs into clear product decisions for leadership.

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Platform: google
Effort: medium

Benefits

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