Job Overview:
Arm is seeking a Principal Product Engineer to lead productization of next-generation high-performance compute (HPC) silicon from pre-silicon readiness through bring-up, qualification, production ramp and HVM. This senior technical role owns cross-functional execution across silicon characterization, performance/power correlation, High-Speed I/O (HSIO), manufacturing test/SLT, yield, reliability and advanced packaging. The successful candidate combines deep silicon expertise with strong product ownership and data-driven execution.
Responsibilities:
• Own end-to-end Product Engineering execution for complex HPC products from product definition through HVM, driving readiness, risk mitigation and technical closure across major milestones.
• Partner with Architecture, Design, DFT/DFX, Validation, Software, Test and Product Management to define productization requirements, silicon observability, characterization plans and manufacturing readiness.
• Lead first-silicon bring-up and PVTF characterization, including Vmin/Fmax, voltage-frequency behavior, leakage, dynamic power, thermal behavior, silicon distributions and production guardbands.
• Drive performance and power correlation from pre-silicon models through silicon and system measurements; translate findings into product limits, binning, fusing and optimized operating points.
• Own HSIO productization and characterization strategy for interfaces such as PCIe/CXL, DDR/LPDDR/HBM, Ethernet/SerDes and die-to-die interconnects, including margining, BER, jitter, eye margin, training/equalization and system-level debug.
• Drive correlation across ATE, bench, SLT and representative platforms, including interactions among silicon, PHY, package, PCB, SI/PI, power delivery, thermal conditions and firmware/software.
• Own manufacturing test and SLT strategy across wafer sort, final test and system-level environments, balancing coverage, outgoing quality, test time and cost.
• Drive yield learning, product limits, qualification, reliability and failure analysis from first silicon through mature HVM; partner with foundry, OSAT and manufacturing/test suppliers on root cause and corrective actions.
• Support advanced 2.5D/3D and chiplet-based productization and establish data-driven product-health metrics for yield, performance, power, HSIO margin, quality and manufacturing stability.
• Provide senior cross-functional technical leadership, communicate complex issues to engineering and leadership teams, and mentor engineers on Product Engineering methodologies and best practices.
Required Skills and Experience :
• Bachelor's, Master's or Ph.D. in Electrical Engineering, Computer Engineering or a related technical discipline, with typically 12+ years of semiconductor industry experience.
• Demonstrated experience bringing multiple complex CPU, GPU, accelerator or SoC products from pre-silicon through production/HVM, preferably on advanced process nodes.
• Deep knowledge of silicon power, performance, voltage, frequency and temperature relationships; hands-on experience with PVTF, Vmin/Fmax, silicon variation and design-to-silicon correlation.
• Strong understanding of semiconductor manufacturing flow, DFT/DFX, wafer sort, final test, SLT, qualification, binning, fusing, guardbanding and HVM yield optimization.
• Working knowledge of HSIO productization, characterization and debug, with experience in one or more of PCIe/CXL, DDR/LPDDR/HBM, Ethernet/SerDes or die-to-die interfaces.
• Ability to analyze large silicon datasets and drive structured root-cause decisions; experience with analytics/scripting tools such as JMP, Silicon.da/Optimal+ or equivalent is valuable.
• Proven ability to lead complex cross-functional technical programs without direct organizational authority, with strong communication and problem-solving skills.
“Nice To Have” Skills and Experience :
• Direct experience with HPC, server-class CPUs, GPUs or AI/ML accelerators, particularly high-core-count/high-power products.
• Experience with 2.5D/3DIC, chiplet architectures, advanced packaging, power delivery and thermal constraints.
• Hands-on HSIO margining/system debug and experience establishing HSIO production screens and SLT coverage.
• Experience with system-level performance, power, thermal and HSIO correlation, telemetry/on-die sensors, and automated product-health analytics.
Leadership Attributes
Product ownership Execution discipline Data-driven decision making | Customer and product focus | Continuous improvement
Please note that no relocation package is available for this role.
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Salary Range:
$249,900-$338,100 per year We value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process.
Our 10x Mindset
At Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: careers.arm.com
Use of AI in Your Application
At Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact accommodations@arm.com so we can support you.
Recruitment Adjustments and Accommodations
At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.
Hybrid Working
Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.
Equal Opportunities
Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Requirements
Must-haves
Own end-to-end Product Engineering execution for complex HPC products from product definition through HVM, driving readiness, risk mitigation and technical closure across major milestones.
Partner with Architecture, Design, DFT/DFX, Validation, Software, Test and Product Management to define productization requirements, silicon observability, characterization plans and manufacturing readiness.
Lead first-silicon bring-up and PVTF characterization, including Vmin/Fmax, voltage-frequency behavior, leakage, dynamic power, thermal behavior, silicon distributions and production guardbands.
Drive performance and power correlation from pre-silicon models through silicon and system measurements; translate findings into product limits, binning, fusing and optimized operating points.
Drive correlation across ATE, bench, SLT and representative platforms, including interactions among silicon, PHY, package, PCB, SI/PI, power delivery, thermal conditions and firmware/software.
Own manufacturing test and SLT strategy across wafer sort, final test and system-level environments, balancing coverage, outgoing quality, test time and cost.
Support advanced 2.5D/3D and chiplet-based productization and establish data-driven product-health metrics for yield, performance, power, HSIO margin, quality and manufacturing stability.
Provide senior cross-functional technical leadership, communicate complex issues to engineering and leadership teams, and mentor engineers on Product Engineering methodologies and best practices.
Bachelor's, Master's or Ph.D. in Electrical Engineering, Computer Engineering or a related technical discipline, with typically 12+ years of semiconductor industry experience.
Demonstrated experience bringing multiple complex CPU, GPU, accelerator or SoC products from pre-silicon through production/HVM, preferably on advanced process nodes.
Deep knowledge of silicon power, performance, voltage, frequency and temperature relationships; hands-on experience with PVTF, Vmin/Fmax, silicon variation and design-to-silicon correlation.
Strong understanding of semiconductor manufacturing flow, DFT/DFX, wafer sort, final test, SLT, qualification, binning, fusing, guardbanding and HVM yield optimization.
Working knowledge of HSIO productization, characterization and debug, with experience in one or more of PCIe/CXL, DDR/LPDDR/HBM, Ethernet/SerDes or die-to-die interfaces.
Ability to analyze large silicon datasets and drive structured root-cause decisions; experience with analytics/scripting tools such as JMP, Silicon.da/Optimal+ or equivalent is valuable.
Proven ability to lead complex cross-functional technical programs without direct organizational authority, with strong communication and problem-solving skills.
Direct experience with HPC, server-class CPUs, GPUs or AI/ML accelerators, particularly high-core-count/high-power products.
Experience with 2.5D/3DIC, chiplet architectures, advanced packaging, power delivery and thermal constraints.
Hands-on HSIO margining/system debug and experience establishing HSIO production screens and SLT coverage.
Experience with system-level performance, power, thermal and HSIO correlation, telemetry/on-die sensors, and automated product-health analytics.
Leadership Attributes
Product ownership Execution discipline Data-driven decision making | Customer and product focus | Continuous improvement
Please note that no relocation package is available for this role.
Our 10x Mindset
Nice-to-haves
“Nice To Have” Skills and Experience :
Application prep
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