Job description

Overview Microsoft is the world’s center of expertise on topological quantum computing.  We are building a scaled, fault‑tolerant quantum computer grounded in topological qubits and integrated end‑to‑end with the Azure Quantum software stack. As a  Quantum Systems Digital Design Engineer II , you’ll collaborate closely with quantum physicists, systems software, RF/EE, and manufacturing/production to define, design, and deliver FPGA‑based, ultra‑low‑latency digital subsystems that sit at the heart of our topological quantum engine—spanning readout classification, error‑decoder acceleration, room‑temperature front‑ends for cryogenic control, high‑speed interconnects, and precision clocking networks. Your work will directly impact logical‑qubit stability, throughput, and system scale. At Microsoft Quantum, we aim to empower science and scientists to solve the world’s biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence, and quantum information technology. Microsoft Quantum will change the world of computing and help solve some of humankind’s currently unsolvable problems. For more information about our team, visit  microsoft.com . Responsibilities • Design & implement RTL for streaming, low ‑ latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/SystemVerilog, including resource/performance trade ‑ offs and power/thermal considerations. • Design and implement high ‑ speed interconnects between subsystems (AXI4/AXI ‑ Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring ‑ up, and throughput/latency tuning. • Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi ‑ domain timing closure, async FIFOs, metastability analysis) for deterministic performance. • Co ‑ design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams; contribute to system ‑ level design reviews. • Verification and validation: develop simulation and constrained ‑ random tests (SV/UVM or equivalent), build on ‑ board diagnostics (ILA/ChipScope), and execute lab bring ‑ up with scopes, VNAs, LA/SC, and RF instruments. • Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign ‑ off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD. • Quality & documentation: produce clear design docs, interface specs, and bring ‑ up guides; participate in rigorous code/design reviews and post ‑ silicon/post ‑ fabrication retros. • Embody our  Culture  and  Values Qualifications Required • Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 1+ years experience in industry or in a research and development environment • OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 2+ years experience in industry or in a research and development environment • OR equivalent experience. • This position requires verification of citizenship or other protected status to meet legal requirements of the role. If the role requires US citizenship, as indicated in the job description, a valid US passport must be provided to verify your citizenship. If the role requires US Person status, as indicated in the job description, US citizens must provide a valid US passport for verification while lawful permanent residents, refugees, and asylees may complete this verification using green cards or other status documents, as applicable. Additional or Preferred Qualifications • 3+ years building production FPGA designs in Verilog/SystemVerilog (or VHDL), including synthesis, P&R, and static timing analysis on Xilinx/AMD (UltraScale+/Versal/RFSoC) and/or Intel platforms. • Proven delivery of low‑latency, streaming datapaths (DSP, filtering, classification, or decoder‑like pipelines) with tight timing closure at high clocks. • Hands‑on with high‑speed I/O and protocols: AXI4/AXIS, JESD204(B/C), Aurora, multi‑gig SERDES; competent in link bring‑up, eye margins, and error budget analysis. • Proficiency in clocking/CDC fundamentals and experience with multi‑clock, multi‑reset systems. • Verification skills (simulation, assertions, testbenches; UVM a plus) and lab debug using ILA/ChipScope, scopes, LA, and RF test gear. • Familiarity with RFSoC architectures (data converters, JESD links) and/or heterogeneous co‑processing with CPUs/GPUs. • Comfort working across HW/SW boundaries (DMA perf tuning, drivers, gRPC/REST control surfaces, telemetry/observability) and with scientific instrumentation. • Experience accelerating decoders (e.g., graph/union‑find/MWPM‑style or LDPC‑class techniques), streaming inference/classification, or similar real‑time algorithms. • Exposure to HLS (C/C++/HLS kernels) and mixed HLS/RTL systems; formal verification. • Background in signal processing/control or quantum control/readout concepts (nice to have; curiosity and fast learning are more important). • Experience with Windows & Linux, VS Code, Git/GitHub, Azure DevOps CI/CD; scripted builds (Tcl/Python); design docs + code reviews + comprehensive testing are part of our quality bar. Other Requirements • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:  • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. • Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. § 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. • Ability to work in an "AI first" environment using modern AI tools to accelerate discovery through hardware development. • Familiarity with designing and building AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval. Quantum Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

Design and implement high ‑ speed interconnects between subsystems (AXI4/AXI ‑ Stream, JESD204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring ‑ up, and throughput/latency tuning.
Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi ‑ domain timing closure, async FIFOs, metastability analysis) for deterministic performance.
Co ‑ design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams; contribute to system ‑ level design reviews.
Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign ‑ off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD.
Quality & documentation: produce clear design docs, interface specs, and bring ‑ up guides; participate in rigorous code/design reviews and post ‑ silicon/post ‑ fabrication retros.
Embody our  Culture  and  Values
Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 1+ years experience in industry or in a research and development environment
OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 2+ years experience in industry or in a research and development environment
OR equivalent experience.
3+ years building production FPGA designs in Verilog/SystemVerilog (or VHDL), including synthesis, P&R, and static timing analysis on Xilinx/AMD (UltraScale+/Versal/RFSoC) and/or Intel platforms.
Proven delivery of low‑latency, streaming datapaths (DSP, filtering, classification, or decoder‑like pipelines) with tight timing closure at high clocks.
Hands‑on with high‑speed I/O and protocols: AXI4/AXIS, JESD204(B/C), Aurora, multi‑gig SERDES; competent in link bring‑up, eye margins, and error budget analysis.
Proficiency in clocking/CDC fundamentals and experience with multi‑clock, multi‑reset systems.
Familiarity with RFSoC architectures (data converters, JESD links) and/or heterogeneous co‑processing with CPUs/GPUs.
Comfort working across HW/SW boundaries (DMA perf tuning, drivers, gRPC/REST control surfaces, telemetry/observability) and with scientific instrumentation.
Experience accelerating decoders (e.g., graph/union‑find/MWPM‑style or LDPC‑class techniques), streaming inference/classification, or similar real‑time algorithms.
Exposure to HLS (C/C++/HLS kernels) and mixed HLS/RTL systems; formal verification.
Experience with Windows & Linux, VS Code, Git/GitHub, Azure DevOps CI/CD; scripted builds (Tcl/Python); design docs + code reviews + comprehensive testing are part of our quality bar.
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Nice-to-haves

Additional or Preferred Qualifications
Verification skills (simulation, assertions, testbenches; UVM a plus) and lab debug using ILA/ChipScope, scopes, LA, and RF test gear.
Background in signal processing/control or quantum control/readout concepts (nice to have; curiosity and fast learning are more important).

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

azurepythonci/cdrestai

Platform: eightfold
Effort: medium