Job description

HRL Laboratories, an IBM company, pioneers the next frontiers of physical and information science. Delivering transformative technologies in automotive, aerospace and defense, HRL advances the critical missions of its customers to help them remove limitations and create competitive advantage. HRL then transitions the work back to customers – ready for real-world application. For more than 70 years, HRL’s rich portfolio of scientific discoveries and engineering innovations continues to build on each other — often in unexpected, profound and far-reaching ways. As a private company owned by IBM, HRL prioritizes purpose over profit, significantly advancing the state of the art. Qubit Systems Laboratory (QSL) is a world leader in semiconductor spin qubits. Our broad expertise spans semiconductor growth, device design and modeling, cryogenic control, high-density interconnects and packaging, quantum architecture, and multiqubit demonstrations. Our system architecture is built entirely around scalable semiconductor manufacturing to make quantum computing affordable for practical business and scientific applications. General Description: You will serve as a technical leader in analog and mixed signal verification for a cutting edge quantum control electronics team, developing silicon that directly enables scalable quantum computing. In this role, you will drive the architecture, integration, and execution of verification solutions for complex cryogenic CMOS circuits. This role blends deep hands‑on modeling and simulation expertise with strategic ownership of verification methodology, ensuring high‑performance, reliable, and manufacturable silicon. You will collaborate across design, modeling, DFT, and validation teams to deliver robust, scalable verification environments. Essential Duties: • Develop and execute analog and mixed-signal (AMS) verification strategies for complex IC designs including ADCs, DACs, PLLs, LDOs, SerDes, and power‑management blocks. • Build and maintain behavioral models using Verilog-A, Verilog‑AMS, real‑number modeling (wreal, SV‑RNM), ensuring accurate abstraction and alignment with transistor‑level implementations. • Perform Spice-level and transistor-level simulations using HSPICE, Spectre, Eldo, and Cadence Virtuoso to validate block‑level and top‑level functionality. • Create and enhance UVM‑AMS and SystemVerilog-based verification environments, including testbench development, stimulus generation, assertion-based verification (SVA/PSL), and coverage-driven methodology. • Develop regression infrastructure and verification dashboards, ensuring thorough functional and analog coverage collection across corners and modes. • Conduct corner-case analysis, Monte Carlo simulations, noise/mismatch analysis, PVT sweeps, and model correlation to guarantee design robustness. • Integrate and verify AMS blocks at the top level using Cadence AMS Designer, Spectre AMS, and Xcelium. • Support DFT strategies for analog/mixed‑signal circuitry, including verification of built‑in test features and coverage metrics. • Collaborate closely with design, modeling, and digital verification teams to ensure alignment between behavioral models and final silicon behavior. • Participate in silicon bring-up, lab debug, and measurement validation, correlating results with simulation data and refining models as needed. • Develop scripts and automation tools (Python, Perl, Tcl, MATLAB) to improve simulation efficiency, regression stability, waveform post-processing, and debugging workflows. • Maintain rigorous version control and continuous integration practices using Git, Jenkins, and related infrastructure. Required Qualifications • Bachelor's, master’s or PhD in Electrical Engineering or related field • 5+ years of experience in analog/mixed-signal verification, AMS modeling, and transistor‑level analysis. • Strong proficiency with Verilog-A, Verilog-AMS, and real-number modeling techniques (wreal, SV‑RNM). • Hands-on experience with Cadence Virtuoso, Spectre, Eldo, HSPICE, Cadence AMS Designer, Spectre AMS, and Xcelium. • Practical experience building SystemVerilog/UVM environments, preferably including UVM‑AMS extensions. • Strong command of assertion-based verification using SVA or PSL. • Solid understanding of analog/mixed-signal systems such as ADCs, DACs, PLLs, LDOs, SerDes, and PMIC architectures. • Demonstrated ability to perform corner analysis, mismatch/Monte Carlo simulations, noise characterization, and behavioral model correlation. • Familiarity with DFT methodologies for AMS blocks and test feature verification. • Experience in lab measurements, silicon debug, and correlating real hardware behavior with simulation. • Proficiency with scripting languages (Python, Perl, Tcl, MATLAB) for automation, data processing, and regression management. • Comfortable working with Git, CI pipelines (e.g., Jenkins), and multi-disciplinary engineering teams. • Strong communication skills, problem-solving ability, and ownership of verification quality from block-level through tape-out and silicon validation. Physical Requirements: Must be sufficiently mobile to work within confined spaces and have both visual and hearing acuity Special Requirements: U.S. Person Status Required Compensation and Benefits: Pay Range : $154,500 - $197,900 Our salary ranges are determined by role, level, and location (California). The range displayed on each job posting reflects the target range for new hire salaries for the position. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range during the hiring process. Benefits: HRL offers a generous and very competitive total compensation and benefits package. Our Regular/Full Time benefits include medical, dental, vision, life insurance, 401K match, gym facilities, PTO, Sick time, upward mobility, and an exciting and challenging work environment. For more information about our company benefit offerings please visit: hrl.com Non-Discrimination and Equal Employment Opportunities (U.S.) Don’t meet every single requirement? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At HRL, we are dedicated to building a diverse, inclusive, and authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles. We are proud to be an EEO/AA employer M/F/D/V. We maintain a drug-free workplace and perform pre-employment substance abuse testing. If you would like more information about Equal Employment Opportunity as an applicant under the law, please go to Employees & Job Applicants | U.S. Equal Employment Opportunity Commission For our privacy policy please visit: www.hrl.com/privacy

Requirements

Must-haves

Develop and execute analog and mixed-signal (AMS) verification strategies for complex IC designs including ADCs, DACs, PLLs, LDOs, SerDes, and power‑management blocks.
Build and maintain behavioral models using Verilog-A, Verilog‑AMS, real‑number modeling (wreal, SV‑RNM), ensuring accurate abstraction and alignment with transistor‑level implementations.
Perform Spice-level and transistor-level simulations using HSPICE, Spectre, Eldo, and Cadence Virtuoso to validate block‑level and top‑level functionality.
Create and enhance UVM‑AMS and SystemVerilog-based verification environments, including testbench development, stimulus generation, assertion-based verification (SVA/PSL), and coverage-driven methodology.
Develop regression infrastructure and verification dashboards, ensuring thorough functional and analog coverage collection across corners and modes.
Conduct corner-case analysis, Monte Carlo simulations, noise/mismatch analysis, PVT sweeps, and model correlation to guarantee design robustness.
Integrate and verify AMS blocks at the top level using Cadence AMS Designer, Spectre AMS, and Xcelium.
Support DFT strategies for analog/mixed‑signal circuitry, including verification of built‑in test features and coverage metrics.
Collaborate closely with design, modeling, and digital verification teams to ensure alignment between behavioral models and final silicon behavior.
Participate in silicon bring-up, lab debug, and measurement validation, correlating results with simulation data and refining models as needed.
Develop scripts and automation tools (Python, Perl, Tcl, MATLAB) to improve simulation efficiency, regression stability, waveform post-processing, and debugging workflows.
Maintain rigorous version control and continuous integration practices using Git, Jenkins, and related infrastructure.
Bachelor's, master’s or PhD in Electrical Engineering or related field
5+ years of experience in analog/mixed-signal verification, AMS modeling, and transistor‑level analysis.
Strong proficiency with Verilog-A, Verilog-AMS, and real-number modeling techniques (wreal, SV‑RNM).
Hands-on experience with Cadence Virtuoso, Spectre, Eldo, HSPICE, Cadence AMS Designer, Spectre AMS, and Xcelium.
Practical experience building SystemVerilog/UVM environments, preferably including UVM‑AMS extensions.
Strong command of assertion-based verification using SVA or PSL.
Solid understanding of analog/mixed-signal systems such as ADCs, DACs, PLLs, LDOs, SerDes, and PMIC architectures.
Demonstrated ability to perform corner analysis, mismatch/Monte Carlo simulations, noise characterization, and behavioral model correlation.
Familiarity with DFT methodologies for AMS blocks and test feature verification.
Experience in lab measurements, silicon debug, and correlating real hardware behavior with simulation.
Proficiency with scripting languages (Python, Perl, Tcl, MATLAB) for automation, data processing, and regression management.
Comfortable working with Git, CI pipelines (e.g., Jenkins), and multi-disciplinary engineering teams.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

pythongo

Platform: lever
Effort: quick

Benefits

Benefits detected in the listing.

Dental

Vision

401k

Pto