Job description

At Nexthop AI, we are searching for an experienced Signal Integrity Engineer to own the high-speed channel design of our next-generation switch platforms. If you've spent your career finding out where the textbook answers stop working, and you want to do that at 224G PAM4 and beyond on hardware that ships, we'd love to have you on our team. About the Role As a Senior Signal Integrity Engineer, you'll be the SI owner for a full platform, with links running at 224G PAM4 per lane and beyond — from concept-phase feasibility, through stackup freeze and design release, into EVT/DVT link bring-up and debug. You'll set the channel targets and loss budgets that the design is built to, drive stackup and material decisions with our fab partners, and be the person the team turns to when a channel doesn't close. You'll also shape the methodology and design rules the rest of the SI team works from, and mentor engineers earlier in their careers. What You'll Do Own signal integrity end to end for one or more switch platforms: pre-layout feasibility, channel architecture, simulation sign-off at design release, and link-performance debug through EVT and DVT. Set high-speed channel targets and loss budgets for links at 224G PAM4 per lane and beyond, and defend them against ASIC SerDes capability, module requirements, and cost and manufacturability constraints. Drive the hardest interconnect problems: ASIC BGA escape design, connector launch optimization, via tuning at frequencies where via electrical length matters, sequential lamination and backdrill strategy, and cascade behavior across the full channel. Own stackup and material strategy with PCB fab vendors — laminate selection, Dk/Df modeling, impedance and loss coupon coverage, multi-vendor alignment, and DFM closure. Run compliance and link analysis (COM, ERL, and the evolving IEEE 802.3dj metrics) for C2M and C2C channels across the module ecosystem we support. Lead correlation between simulation, coupon data, and system measurement — VNA, TDR, high-speed scopes, BERT, and the ASIC's built-in SerDes diagnostics (internal eye scans, pre-FEC BER, equalizer settings) — and drive root cause when they disagree. Work directly with ASIC, connector, and package vendors on models, launch geometry, and specifications; hold them to what we need. Improve how the team works: simulation automation in Python, reusable analysis flows, routing and via design rules, and the SI requirements our hardware and layout partners design against. Mentor junior SI engineers, review their analysis, and participate in hiring. What We're Looking For Technical Expertise MS or PhD in Electrical Engineering, Physics, or a related field (BS with equivalent depth considered), with 10-15 years of signal integrity experience on high-speed system design. Proven track record owning SI for complex boards through to production — ideally high pin-count, high-power ASIC designs at 50G/lane or above. Deep expertise in 3D EM simulation and extraction: HFSS, SIwave, Sigrity, ADS, or equivalent, including model correlation to measurement. Command of differential and mixed-mode S-parameters, mode conversion, crosstalk attribution, and time-domain analysis — and the physics behind the anomalies. Experience with link budgeting and compliance methodology for high-speed Ethernet (COM, ERL, IEEE 802.3ck / 802.3dj or comparable), including C2M channel definition. Hands-on knowledge of PCB stackup design, low-loss materials, and fabrication process capability and its variation. Strong Python skills for simulation automation and large-scale data analysis. Nice to Have 224G PAM4 / 200G-per-lane channel design experience. Participation in IEEE 802.3 or OIF standards work. Experience with cabled and optical module ecosystems (OSFP, QSFP-DD, DAC/ACC/AEC/LPO/LRO). Power integrity or EMC breadth alongside SI. Experience building an SI methodology or team from an early stage. Hands-On Skills Designing and validating via and launch structures against measured data, not just simulation. High-speed measurement and de-embedding, including fixture design and calibration strategy. Reading layout critically and giving layout and hardware engineers actionable, prioritized feedback. Soft Skills Takes ownership of outcomes, not just analyses — you close problems rather than reporting them. Can "do what it takes to succeed" and be a team player simultaneously. Exceptional communication: able to explain a channel risk to an ASIC vendor, a layout engineer, and an executive on the same day. Sound engineering judgment under schedule pressure, with a clear view of technical risk and tradeoffs. Generous with what you know — you make the engineers around you better. Location This role is based in our Bay Area office. Platform ownership at Nexthop includes hands-on lab correlation and bring-up work, so we expect regular onsite presence. Why Join Us? At Nexthop AI, we believe in pushing boundaries and turning ideas into reality. You'll be a technical owner on products built for the largest AI deployments in the world, working at the edge of what copper interconnect can deliver, alongside a team that has shipped datacenter networking hardware at scale. The problems here don't have published answers yet. Let's build something extraordinary together. Ready to make an impact? Apply now and take your career to the next level!

Requirements

Must-haves

Own signal integrity end to end for one or more switch platforms: pre-layout feasibility, channel architecture, simulation sign-off at design release, and link-performance debug through EVT and DVT.
Set high-speed channel targets and loss budgets for links at 224G PAM4 per lane and beyond, and defend them against ASIC SerDes capability, module requirements, and cost and manufacturability constraints.
Own stackup and material strategy with PCB fab vendors — laminate selection, Dk/Df modeling, impedance and loss coupon coverage, multi-vendor alignment, and DFM closure.
Run compliance and link analysis (COM, ERL, and the evolving IEEE 802.3dj metrics) for C2M and C2C channels across the module ecosystem we support.
Work directly with ASIC, connector, and package vendors on models, launch geometry, and specifications; hold them to what we need.
Improve how the team works: simulation automation in Python, reusable analysis flows, routing and via design rules, and the SI requirements our hardware and layout partners design against.
Mentor junior SI engineers, review their analysis, and participate in hiring.
Technical Expertise
MS or PhD in Electrical Engineering, Physics, or a related field (BS with equivalent depth considered), with 10-15 years of signal integrity experience on high-speed system design.
Proven track record owning SI for complex boards through to production — ideally high pin-count, high-power ASIC designs at 50G/lane or above.
Deep expertise in 3D EM simulation and extraction: HFSS, SIwave, Sigrity, ADS, or equivalent, including model correlation to measurement.
Command of differential and mixed-mode S-parameters, mode conversion, crosstalk attribution, and time-domain analysis — and the physics behind the anomalies.

Nice-to-haves

224G PAM4 / 200G-per-lane channel design experience.
Participation in IEEE 802.3 or OIF standards work.
Experience with cabled and optical module ecosystems (OSFP, QSFP-DD, DAC/ACC/AEC/LPO/LRO).
Power integrity or EMC breadth alongside SI.
Experience building an SI methodology or team from an early stage.
Hands-On Skills
Designing and validating via and launch structures against measured data, not just simulation.
High-speed measurement and de-embedding, including fixture design and calibration strategy.
Reading layout critically and giving layout and hardware engineers actionable, prioritized feedback.
Takes ownership of outcomes, not just analyses — you close problems rather than reporting them.
Can "do what it takes to succeed" and be a team player simultaneously.
Exceptional communication: able to explain a channel risk to an ASIC vendor, a layout engineer, and an executive on the same day.

Application prep

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