Job description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Engineer will be responsible for verification of complex switch designs. Responsibilities will include creating SystemVerilog-based verification environments (testbenches, checkers, transactors) as well as creating and executing testplans for verifications of RTL and gatesim-based designs at both the block and chip level. The engineer will also be tasked with creating ATE testing vectors, as well as C-based diagnostic tests to be run on the actual silicon. Job Requirements: A Master s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent A minimum of 6 years of work experience in Design Verification Strong knowledge and hands-on experience in verification methods, tools and environment Strong programming skills, including in System Verilog and scripts languages Knowledge and experience in UVM methodology is preferable Knowledge of networking and switching concept is a plus Additional Job Description: Compensation and Benefits The annual base salary range for this position is $108,000 - $172,800 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Requirements

Must-haves

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A Master s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
A minimum of 6 years of work experience in Design Verification
Strong knowledge and hands-on experience in verification methods, tools and environment
Strong programming skills, including in System Verilog and scripts languages
Knowledge and experience in UVM methodology is preferable

Nice-to-haves

Knowledge of networking and switching concept is a plus

Application prep

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Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)