Job description

Position Overview We are seeking an experienced Hardware Engineer or Architect to join our team in Hillsboro, OR, specializing in technical analysis of AI and datacenter hardware. This role involves analyzing product architecture, design, and manufacturing processes, and being an active contributor in the planning, tools, and processes required to acquire this information. This role requires a mix of technical expertise, design sensibility, and autonomy. You'll need to work independently, collaborate across our globally distributed team, and examine and report on the design choices, optimizations, and trade-offs in competing hardware, translating physical analysis into actionable insights. The role rewards curiosity. The strongest people in this work are drawn to investigation — taking apart what they could have helped design, connecting physical evidence to architectural intent and roadmap signals, and following threads beyond any single prior role. Responsibilities • Conduct detailed architectural analysis of AI and datacenter hardware — GPUs, ASICs, CPUs, custom accelerators, high-speed I/O, memory subsystems, and their packaging. • Drive end-to-end teardown and characterization; operate the analytical toolchain and direct more specialized work as needed. • Identify competitive advantages, disadvantages, and generational changes in hardware design, packaging, and system-level decisions. • Apply Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) reasoning to interpret architectural trade-offs and process-design interactions. • Co-author technical research published by SemiAnalysis — physical observation, cross-industry context, and argument all in your words. • Contribute to the growth and expansion of the lab's capabilities and output; bring your unique skills to a strong and expansive team. Requirements • 3+ years in hardware architecture, product design, silicon engineering, post-silicon debug, or closely equivalent, with genuine exposure to leading-edge parts. • Strong functional knowledge of AI and datacenter hardware architecture (GPUs, CPUs, accelerators) on advanced process nodes. • Direct experience in physical or electrical failure analysis, fault isolation, device debug, or related physical root-cause work. • Understanding of Design Technology Co-Optimization (DTCO) principles. • Hands-on experience with, or strong aptitude for, semiconductor sample preparation and analytical tools — precision polishing, FIB, SEM, and related electron-beam, X-ray, and compositional methods. Nice to Have • Product design or manufacturing R&D in advanced packaging (2.5D / 3D, high-speed interconnects, hybrid bonding). • Broad understanding of advanced manufacturing across CMOS logic, memory, and emerging technologies. • Interpreting micrographs and electrical measurements to infer design and process characteristics. • Comfort developing plans for physical and electrical FA toolchains. • Python for data analysis and engineering tasks. • Strong professional network of experts. • Statistical and process-control literacy. What Makes Someone Great • Architectural fluency — CPU / GPU / ASIC floor planning, memory hierarchy, and advanced I/O are native language for you. • Cross-industry context — you place any architectural choice against vendor and competitor history without reaching for a reference. • Physical intuition , or willingness to build it fast — you know what is real and what is artifact. • Written argument — your technical writing holds up under expert scrutiny. • Curiosity and ownership — you're drawn to investigate; you ship and close your own loops. • Agency — you deliver on your responsibilities and support others in theirs. You treat everyone you work with as a peer and leave concepts of hierarchy at the door. Location & Authorization 95% onsite in Hillsboro, OR. US work authorization required; no visa sponsorship. Competitive compensation commensurate with experience. Growth Area • Deepen expertise in next-generation AI hardware architectures, including custom accelerators, chiplet-based designs, and heterogeneous compute systems. • Expand capabilities in advanced packaging and interconnect technologies (e.g., 2.5D/3D integration, HBM, optical interconnects) and their system-level implications. • Develop stronger cross-layer understanding from device physics and manufacturing processes through system architecture and workload optimization. • Build proficiency in data-driven hardware analysis, including benchmarking, performance modeling, and automated analysis using Python and related tools. • Strengthen collaboration with research, manufacturing, and market teams to translate technical findings into high-impact strategic insights. • Enhance external engagement through interaction with industry experts, conference participation, and contribution to thought leadership. • Progress toward a senior architect or subject matter expert role with influence over research direction, technical coverage, and industry perspective.

Requirements

Must-haves

Position Overview
Conduct detailed architectural analysis of AI and datacenter hardware — GPUs, ASICs, CPUs, custom accelerators, high-speed I/O, memory subsystems, and their packaging.
Drive end-to-end teardown and characterization; operate the analytical toolchain and direct more specialized work as needed.
Identify competitive advantages, disadvantages, and generational changes in hardware design, packaging, and system-level decisions.
Apply Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) reasoning to interpret architectural trade-offs and process-design interactions.
Co-author technical research published by SemiAnalysis — physical observation, cross-industry context, and argument all in your words.
Contribute to the growth and expansion of the lab's capabilities and output; bring your unique skills to a strong and expansive team.
3+ years in hardware architecture, product design, silicon engineering, post-silicon debug, or closely equivalent, with genuine exposure to leading-edge parts.
Strong functional knowledge of AI and datacenter hardware architecture (GPUs, CPUs, accelerators) on advanced process nodes.
Direct experience in physical or electrical failure analysis, fault isolation, device debug, or related physical root-cause work.
Understanding of Design Technology Co-Optimization (DTCO) principles.
Hands-on experience with, or strong aptitude for, semiconductor sample preparation and analytical tools — precision polishing, FIB, SEM, and related electron-beam, X-ray, and compositional methods.

Nice-to-haves

Product design or manufacturing R&D in advanced packaging (2.5D / 3D, high-speed interconnects, hybrid bonding).
Broad understanding of advanced manufacturing across CMOS logic, memory, and emerging technologies.
Interpreting micrographs and electrical measurements to infer design and process characteristics.
Comfort developing plans for physical and electrical FA toolchains.
Python for data analysis and engineering tasks.
Strong professional network of experts.
Statistical and process-control literacy.
What Makes Someone Great
Architectural fluency — CPU / GPU / ASIC floor planning, memory hierarchy, and advanced I/O are native language for you.
Cross-industry context — you place any architectural choice against vendor and competitor history without reaching for a reference.
Physical intuition , or willingness to build it fast — you know what is real and what is artifact.
Written argument — your technical writing holds up under expert scrutiny.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipython

Platform: careers-page
Effort: medium