Job description

• Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle. • Work with the physical design team to drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress. • Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Minimum BS and 10+ years of relevant industry experience Needs to be familiar with aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration. Experience with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions. Familiar with a hierarchical design approach, top-down design, budgeting, timing and physical convergence. Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain is required. Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative sub 45nm technologies. A detailed understanding of database management issues is required. From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows is required. Familiar with various process-related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.

Requirements

Must-haves

Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
Work with the physical design team to drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
Minimum BS and 10+ years of relevant industry experience
Needs to be familiar with aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
Experience with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
Familiar with a hierarchical design approach, top-down design, budgeting, timing and physical convergence.
Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain is required.
Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative sub 45nm technologies.
A detailed understanding of database management issues is required.
From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows is required.
Familiar with various process-related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: apple
Effort: medium