Job description

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a Senior Staff GPU Physical Design Engineer, you will help shape the physical implementation and methodology innovation for high-performance GPU and system-level IP, enabling market-differentiating power, performance, and area (PPA) goals across Samsung’s advanced technology nodes. Your work will impact implementation quality, silicon readiness, and scalable execution for next-generation GPU IPs. In this senior individual contributor role, you will contribute to key stages of the physical design flow, from synthesis through floorplanning, timing closure, and signoff, while help advancing implementation strategies, methodology innovation, and scalable execution across parallel development cycles. You will collaborate closely with hardware, advanced design technology, and system-level teams to resolve complex implementation challenges and deliver robust, high-quality silicon for advanced-node designs. Leveraging your expertise in one or more technical areas, you help shape full-chip and block-level implementation, including floorplanning, placement, routing, timing closure, and signoff for complex GPU and SoC designs. You contribute to implementation strategies to achieve market-differentiating PPA targets, including power optimization, congestion management, STA-driven convergence, and reliability considerations across advanced-node designs. You help advancing methodology and flow innovation, including automation, tool optimization, and scalable design practices to improve implementation quality, productivity, and repeatability across projects. You enable cross-functional collaboration with architecture, RTL, advanced design technology, software, system-level teams, and external vendors, to adapt physical design flows for cutting-edge nodes and accelerate resolution of complex implementation and tool challenges. You inspire high performance by mentoring junior engineers, fostering a culture of ownership, accountability and innovation, and promoting continuous learning by staying ahead of physical design innovation for emerging GPU technologies. Skills and Qualifications 11 years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9 years of experience with a Master’s Degree, or 7 years of experience with a Ph.D. 7 years of hands-on experience with full physical design implementation flows, including synthesis, place-and-route, clock tree synthesis (CTS), timing closure, and signoff. Strong expertise in physical design implementation for complex GPU or SoC designs, including low-power design, physical verification (DRC/LVS), and advanced-node challenges Strong experience with timing analysis and convergence methodologies, including STA, signal integrity, and reliability considerations Strong proficiency with industry-standard EDA tools (Synopsys or Cadence: ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC) Strong scripting and automation skills in Python, Tcl, Shell, or Perl Strong analytical, debugging, and problem-solving skills with a data-driven approach for complex flow and design challenges Experience with leading technical initiatives, driving process and methodology innovation, and mentoring engineers. Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast-paced, global team environment. Preferred Qualifications Experience with advanced-node designs (≤5nm) and high-performance GPU or SoC programs Experience with DTCO methodologies and implementation scalability challenges Our Team The Advanced Design Technology and Design Implementation teams play a critical role in enabling GPU and system-level development within Samsung SARC/ACL and the broader System LSI organization. Operating at the intersection of design technology and physical implementation, we partner closely with Foundry from early technology exploration through the full development cycle. Spanning advanced design methodologies, GPU physical design, CAD, and DTCO, we accelerate adoption of leading technology nodes and deliver optimized power, performance, area (PPA), silicon quality, and turnaround time for next-generation IP solutions. You will join a highly collaborative, fast-paced environment working across parallel development cycles with direct impact on consumer technologies used worldwide. Here, you’ll help build what’s next: experimenting with new ideas, broadening your technical expertise, and solving impactful challenges alongside talented teammates who value ownership, continuous learning, and growth. Total Rewards At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,200 and $270,400. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance. Additionally, this role might be eligible to participate in long term incentive plan and relocation. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA). Trade Secrets By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity. U.S. Export Control This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization. #SARC * Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here . * Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Requirements

Must-haves

Role and Responsibilities
Leveraging your expertise in one or more technical areas, you help shape full-chip and block-level implementation, including floorplanning, placement, routing, timing closure, and signoff for complex GPU and SoC designs.
You help advancing methodology and flow innovation, including automation, tool optimization, and scalable design practices to improve implementation quality, productivity, and repeatability across projects.
Skills and Qualifications
11 years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9 years of experience with a Master’s Degree, or 7 years of experience with a Ph.D.
7 years of hands-on experience with full physical design implementation flows, including synthesis, place-and-route, clock tree synthesis (CTS), timing closure, and signoff.
Strong expertise in physical design implementation for complex GPU or SoC designs, including low-power design, physical verification (DRC/LVS), and advanced-node challenges
Strong experience with timing analysis and convergence methodologies, including STA, signal integrity, and reliability considerations
Strong proficiency with industry-standard EDA tools (Synopsys or Cadence: ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC)
Strong scripting and automation skills in Python, Tcl, Shell, or Perl
Strong analytical, debugging, and problem-solving skills with a data-driven approach for complex flow and design challenges
Experience with leading technical initiatives, driving process and methodology innovation, and mentoring engineers.
Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast-paced, global team environment.
Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here .

Nice-to-haves

Experience with advanced-node designs (≤5nm) and high-performance GPU or SoC programs
Experience with DTCO methodologies and implementation scalability challenges

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python

Platform: workday
Effort: long

Benefits

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Dental

Vision

401(K)

Paid Time Off

Wellness