Job description

About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off. You will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market. Key Responsibilities - Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII. - Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation. - Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna). - Generate abstracts, views, and timing budgets for clean hierarchical integration of your blocks into the top level. - Collaborate with RTL Designers and provide Physical Design feedback to improve PPA. - Continuously improve the PPA of owned blocks and contribute learnings back into the shared RTL-to-GDSII flow. - Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks. You may be a good fit if you have - 5-10+ years of previous experience with PD - Tools, flow, and design methodology from RTL synthesis to GDSII sign-off - Experience with back-end design and timing closure on advanced process nodes (5nm and below) - Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows - Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.) - Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis - Scripting ability in Tcl, Python, or Perl for flow automation and debug - Deeply creative and able to think from first principles Strong candidates may also have experience with - Familiarity with modern ML and LLM model architectures - Ability to program with Python or another scripting language - Familiarity with AI tools for programming/coding - Startup experience or comfort working in fast-paced environments Benefits - Medical, dental, and vision packages with generous premium coverage - $500 per month credit for waiving medical benefits - Housing subsidy of $2.5k per month for those living within walking distance of the office - Relocation support for those moving to San Jose (Santana Row) - Various wellness benefits covering fitness, mental health, and more - Daily lunch and dinner in our office - Unlimited compute budget subject to ROI justification How we’re different Etched believes in the Bitter Lesson incompleteideas.net. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

Requirements

Must-haves

Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII.
Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation.
Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna).
Generate abstracts, views, and timing budgets for clean hierarchical integration of your blocks into the top level.
Collaborate with RTL Designers and provide Physical Design feedback to improve PPA.
Continuously improve the PPA of owned blocks and contribute learnings back into the shared RTL-to-GDSII flow.
Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks.
You may be a good fit if you have
5-10+ years of previous experience with PD
Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
Scripting ability in Tcl, Python, or Perl for flow automation and debug
Deeply creative and able to think from first principles
Strong candidates may also have experience with
Familiarity with modern ML and LLM model architectures
Ability to program with Python or another scripting language
Familiarity with AI tools for programming/coding
Startup experience or comfort working in fast-paced environments

Nice-to-haves

None flagged.

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Benefits

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Dental

Vision

Wellness