Job description

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google . • Partner with cross-functional teams to architect, implement, and verify design-for-test (DFT) solutions for advanced CPU designs. • Pioneer custom DFT methodologies using industry-standard EDA tools to accelerate turnaround times and test coverage. • Develop, debug, and optimize production test patterns for automatic test equipment flows to support silicon delivery. • Mentor peers and foster cross-functional engineering collaboration across the DFT organization. • Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. • 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows. • Experience developing, deploying, and supporting DFT flows ( ATPG, Logic Vision, BIST, or JTAG). Minimum qualifications: • Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. • 8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows. • Experience developing, deploying, and supporting DFT flows ( ATPG, Logic Vision, BIST, or JTAG). Preferred qualifications: • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field. • Experience applying AI/ML-assisted DFT design techniques for scaling and physical design closure. • Experience with scripting in Python, Tcl, or Perl, and data mining for QoR metrics. • Experience developing novel DFT solutions, silicon bring-up, and validation. • Knowledge of high-performance, low-power design DFT techniques and end-to-end silicon flows.

Requirements

Must-haves

Learn more about benefits at Google .
Partner with cross-functional teams to architect, implement, and verify design-for-test (DFT) solutions for advanced CPU designs.
Pioneer custom DFT methodologies using industry-standard EDA tools to accelerate turnaround times and test coverage.
Develop, debug, and optimize production test patterns for automatic test equipment flows to support silicon delivery.
Mentor peers and foster cross-functional engineering collaboration across the DFT organization.
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
Experience developing, deploying, and supporting DFT flows ( ATPG, Logic Vision, BIST, or JTAG).
Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
8 years of experience in high-performance IP or SoC Design For Test (DFT) activities and flows.
Experience developing, deploying, and supporting DFT flows ( ATPG, Logic Vision, BIST, or JTAG).

Nice-to-haves

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
Experience applying AI/ML-assisted DFT design techniques for scaling and physical design closure.
Experience with scripting in Python, Tcl, or Perl, and data mining for QoR metrics.
Experience developing novel DFT solutions, silicon bring-up, and validation.
Knowledge of high-performance, low-power design DFT techniques and end-to-end silicon flows.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aimlpython

Platform: google
Effort: medium

Benefits

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