Job description

Join the leading chiplet startup! As the Director of Design Verification at Eliyan, you will lead and scale a high-performing verification team at a fast-paced startup creating technologies that fuel tomorrow’s chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will own the end-to-end verification strategy across multiple PHY and controller products, spanning link layer, PCS, PMA, forward error correction, and analog/mixed-signal verification flows. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits. Key Responsibilities: Define and own the verification strategy and methodology across multiple PHY and controller product lines, including D2D, UCIe, and Ethernet interfaces Build, mentor, and manage a world-class verification team; establish best practices for UVM-based environments, coverage-driven verification, and formal methods Drive verification planning and execution for link layer, PCS, PMA, forward error correction (FEC), auto-negotiation, and link training subsystems Establish and champion analog/mixed-signal (AMS) verification flows, including real-number modeling (RNM), SVAMS co-simulation strategies, and integration of AMS behavioral models into digital verification environments Partner with design, architecture, DFT, and physical design teams to drive micro-architecture reviews, test-plan completeness, and functional/code/assertion coverage closure Own verification milestones and deliverables across multiple concurrent tapeout programs; track progress, manage risk, and report status to executive leadership Drive continuous improvement in verification infrastructure including regression frameworks, CI/CD integration, coverage analytics, and productivity tooling Ensure IP compliance with relevant industry standards including IEEE 802.3, UCIe, and emerging D2D interconnect specifications Evaluate, integrate, and manage 3rd party VIPs and AMS verification IP; coordinate feature/bug tracking and vendor relationships Oversee development of DPI-based firmware co-simulation environments and system-level verification strategies for PHY bring-up and validation Oversee GLS environments for functional, timing, and power-aware simulations; drive signoff quality for tapeout readiness Qualifications: Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields 15+ years of experience in design verification of high-speed serial interfaces, PHYs, and controller IPs, with at least 5 years in a people-management or leadership role Deep expertise in SystemVerilog/UVM methodology, constrained-random verification, assertion-based verification, and formal verification techniques Demonstrated experience with AMS verification methodologies including real-number modeling (RNM), Verilog-AMS, SVAMS co-simulation, and mixed-signal behavioral modeling Strong working knowledge of link layer protocols, PCS architectures (including FEC — RS-FEC, KP4, KR4), Ethernet 802.3 clauses for 100G/200G/400G/800G, and die-to-die interconnect standards such as UCIe Proven ability to drive verification innovation including automation, AI/ML-assisted verification, and scalable methodologies that improve team productivity and product quality Hands-on experience verifying mixed-signal IPs (PLLs, CDRs, SerDes analog front-ends, DLLs) and integrating analog models into digital verification environments Track record of successfully building and scaling verification teams in startup or high-growth environments with multiple concurrent tapeouts Experience with DRAM Controllers/PHYs, HBM memory interfaces, and/or optical interconnect verification a plus

Requirements

Must-haves

Define and own the verification strategy and methodology across multiple PHY and controller product lines, including D2D, UCIe, and Ethernet interfaces
Build, mentor, and manage a world-class verification team; establish best practices for UVM-based environments, coverage-driven verification, and formal methods
Drive verification planning and execution for link layer, PCS, PMA, forward error correction (FEC), auto-negotiation, and link training subsystems
Establish and champion analog/mixed-signal (AMS) verification flows, including real-number modeling (RNM), SVAMS co-simulation strategies, and integration of AMS behavioral models into digital verification environments
Partner with design, architecture, DFT, and physical design teams to drive micro-architecture reviews, test-plan completeness, and functional/code/assertion coverage closure
Own verification milestones and deliverables across multiple concurrent tapeout programs; track progress, manage risk, and report status to executive leadership
Drive continuous improvement in verification infrastructure including regression frameworks, CI/CD integration, coverage analytics, and productivity tooling
Ensure IP compliance with relevant industry standards including IEEE 802.3, UCIe, and emerging D2D interconnect specifications
Evaluate, integrate, and manage 3rd party VIPs and AMS verification IP; coordinate feature/bug tracking and vendor relationships
Oversee development of DPI-based firmware co-simulation environments and system-level verification strategies for PHY bring-up and validation
Oversee GLS environments for functional, timing, and power-aware simulations; drive signoff quality for tapeout readiness
Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
15+ years of experience in design verification of high-speed serial interfaces, PHYs, and controller IPs, with at least 5 years in a people-management or leadership role
Deep expertise in SystemVerilog/UVM methodology, constrained-random verification, assertion-based verification, and formal verification techniques
Demonstrated experience with AMS verification methodologies including real-number modeling (RNM), Verilog-AMS, SVAMS co-simulation, and mixed-signal behavioral modeling
Strong working knowledge of link layer protocols, PCS architectures (including FEC — RS-FEC, KP4, KR4), Ethernet 802.3 clauses for 100G/200G/400G/800G, and die-to-die interconnect standards such as UCIe
Proven ability to drive verification innovation including automation, AI/ML-assisted verification, and scalable methodologies that improve team productivity and product quality
Hands-on experience verifying mixed-signal IPs (PLLs, CDRs, SerDes analog front-ends, DLLs) and integrating analog models into digital verification environments
Track record of successfully building and scaling verification teams in startup or high-growth environments with multiple concurrent tapeouts

Nice-to-haves

Experience with DRAM Controllers/PHYs, HBM memory interfaces, and/or optical interconnect verification a plus

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

ci/cdaiml

Platform: lever
Effort: quick