Job description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Develop and implement DFT (Design For Test) architecture and document DFT specifications. Implement DFT infrastructure. Code Verilog Register Transfer Language (RTL) for DFT logic. Collaborate with designers to integrate DFT implementations and run various checks. Partner with designers on STA (Static Timing Analysis), physical, power and logical issues. Coordinate with DV (Design Verification) team to verify DFT implementations in RTL and Gate level, review verification coverage and implement ECOs (Engineering Change Orders). Generate ATPG (Automatic Test Patten Generation) structural test vectors and analyze and improve test coverage. Engage with test engineers to debug and bring up test vectors on silicon. Support TTR (Test time Reduction) and silicon diagnosis efforts. Handle schedules and support multi-functional engineering efforts. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $146,717 - $218,000/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: apple.com. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation. Experience and/or education must include: Designing and verifying RTL using Verilog hardware description language. Knowledge of MBIST, march algorithms and memory fault models. Designing Joint Test Action Group (JTAG) architecture and programming DFT control registers for chip testing Automating DFT design flows using Python or Perl scripting languages Knowledge of STA for timing analysis. Running RTL and gate-level simulations using industry-standard tools such as VCS or NCSIM to debug and resolve design issues Utilizing Automatic Test Pattern Generation (ATPG) tools for scan pattern generation and fault coverage analysis across various fault models Performing silicon failure diagnosis and analysis from Automated Test Equipment (ATE) to improve yield and manufacturing processes Applying low-power design techniques to reduce overall chip power consumption N/A

Requirements

Must-haves

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation.
Designing and verifying RTL using Verilog hardware description language.
Knowledge of MBIST, march algorithms and memory fault models.
Designing Joint Test Action Group (JTAG) architecture and programming DFT control registers for chip testing
Automating DFT design flows using Python or Perl scripting languages
Knowledge of STA for timing analysis.
Running RTL and gate-level simulations using industry-standard tools such as VCS or NCSIM to debug and resolve design issues
Utilizing Automatic Test Pattern Generation (ATPG) tools for scan pattern generation and fault coverage analysis across various fault models
Performing silicon failure diagnosis and analysis from Automated Test Equipment (ATE) to improve yield and manufacturing processes
Applying low-power design techniques to reduce overall chip power consumption

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: apple
Effort: medium

Benefits

Benefits detected in the listing.

Dental