Job description

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today s innovators stay Ahead of What s Possible. Learn more at www.analog.com and on LinkedIn and X . The Position: Analog Devices is seeking a Principal Analog/Mixed-Signal IC Design Engineer for its Data Center & Energy (DCE) group in Wilmington, MA. Within DCE, we develop high-reliability power, connectivity, and analytics solutions for hyperscale data center platforms: mixed-signal SoCs combining precision analog front-ends, high-speed data converters, and embedded processing in advanced FinFET process technologies. The successful candidate will lead analog and mixed-signal circuit design from architecture through silicon validation in deep submicron FinFET processes. This is a principal-level role: a recognized technical authority who drives system-level tradeoffs and whose design decisions directly impact product performance, power, area, and manufacturability. The role carries both hands-on design ownership and technical leadership of junior and senior engineers. This is a hands-on technical leadership position with significant breadth, spanning precision voltage sensing, high-speed data conversion, power regulation, and mixed-signal integration. The team works across multiple process nodes and product generations in a collaborative, fast-paced environment. Analog Devices rewards performance, innovation, and technical depth. Responsibilities include, but are not limited to: Own analog architecture and circuit design for complex mixed-signal SoC subsystems: precision voltage sense paths, high-speed and low-speed ADC front-ends, voltage references, regulators, bias generation, and I/O interfaces Transistor-level design, simulation, and optimization in deep submicron FinFET processes; management of device-level tradeoffs (leakage, mismatch, reliability, electromigration) Drive system-level analog/digital partitioning decisions; define and validate specifications at the block, subsystem, and SoC level Lead mixed-signal verification including behavioral modeling, co-simulation with digital, and corner/Monte Carlo analysis Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability; support silicon bring-up, characterization, and debug Provide technical mentorship and design review leadership; establish reusable IP and best practices Collaborate with cross-functional teams (architecture, digital, firmware, applications, customers) to translate system requirements into analog specifications and robust, manufacturable solutions Contribute to product roadmaps, patent portfolio, and ADI s analog design methodology improvements Qualifications/Experience: The ideal candidate combines deep analog circuit design expertise with hands-on experience in FinFET process technologies. They are self-directed, technically rigorous, and comfortable leading design tradeoffs in a multi-disciplinary SoC environment. MSEE or PhD preferred; BSEE with 12 years of analog/mixed-signal IC design experience considered Demonstrated track record of silicon-proven designs in deep submicron FinFET processes; deep understanding of device physics, mismatch, leakage management, and reliability at advanced nodes Experience designing precision analog circuits: voltage references, regulators, ADC front-ends, bias generators, comparators, or similar Proficiency with industry EDA tools (Cadence Virtuoso, Spectre, AMS simulation environments) Experience taking designs from specification through layout, tapeout, silicon bring-up, and production release Strong written and verbal communication skills; ability to present design reviews and technical tradeoffs to cross-functional audiences Experience mentoring engineers and leading design reviews Familiarity with DFT, production test, and design-for-manufacturability practices in advanced CMOS For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law . Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days The expected wage range for a new hire into this position is $157,080 to $227,460. Actual wage offered may vary depending on work location , experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time , and other benefits.

Requirements

Must-haves

Responsibilities include, but are not limited to:
Transistor-level design, simulation, and optimization in deep submicron FinFET processes; management of device-level tradeoffs (leakage, mismatch, reliability, electromigration)
Drive system-level analog/digital partitioning decisions; define and validate specifications at the block, subsystem, and SoC level
Lead mixed-signal verification including behavioral modeling, co-simulation with digital, and corner/Monte Carlo analysis
Collaborate with layout, DFT, and test engineering to ensure robust DFM and production testability; support silicon bring-up, characterization, and debug
Provide technical mentorship and design review leadership; establish reusable IP and best practices
Collaborate with cross-functional teams (architecture, digital, firmware, applications, customers) to translate system requirements into analog specifications and robust, manufacturable solutions
Contribute to product roadmaps, patent portfolio, and ADI s analog design methodology improvements
Demonstrated track record of silicon-proven designs in deep submicron FinFET processes; deep understanding of device physics, mismatch, leakage management, and reliability at advanced nodes
Experience designing precision analog circuits: voltage references, regulators, ADC front-ends, bias generators, comparators, or similar
Proficiency with industry EDA tools (Cadence Virtuoso, Spectre, AMS simulation environments)
Experience taking designs from specification through layout, tapeout, silicon bring-up, and production release
Strong written and verbal communication skills; ability to present design reviews and technical tradeoffs to cross-functional audiences
Experience mentoring engineers and leading design reviews
Familiarity with DFT, production test, and design-for-manufacturability practices in advanced CMOS
EEO is the Law: Notice of Applicant Rights Under the Law .
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days

Nice-to-haves

MSEE or PhD preferred; BSEE with 12 years of analog/mixed-signal IC design experience considered

Application prep

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Keywords to mirror

aigo

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401k