Job description

The main responsibility of this role is to drive the SOC power simulation, optimization and modeling. • Work with cross functional teams, including architecture, RTL and physical design teams, to determine the interesting use-cases to simulate power, to provide power projections and targets for the future projects, and to improving the SOC power efficiency • Working with SOC power team members to drive power analysis and optimization tasks, improving the efficiency with automation and GenAI/LLM approaches. • Explore new methodology to analyze the power data, create power metrics to identify the optimization opportunities, drive automated approach to improve SOC power efficiency across IPs • Collaborate cross-functional teams to deploy the power optimization to improve SOC power, review results, improve the methodology on efficiency, runtime, and support boarder scope of designs. A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience. Familiarity with ASIC power analysis and optimization Familiarity with machine learning algorithms and programming Familiarity with Verilog and System Verilog. Familiarity with SOC design flow and methodology Familiarity with scripting in Python. Familiarity computer architecture, logic and circuits design Familiarity signal processing is a plus Silicon power measurement experience is a plus SOC power modeling, low power design and power optimization experience is a plus Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups

Requirements

Must-haves

The main responsibility of this role is to drive the SOC power simulation, optimization and modeling.
Working with SOC power team members to drive power analysis and optimization tasks, improving the efficiency with automation and GenAI/LLM approaches.
Explore new methodology to analyze the power data, create power metrics to identify the optimization opportunities, drive automated approach to improve SOC power efficiency across IPs
Collaborate cross-functional teams to deploy the power optimization to improve SOC power, review results, improve the methodology on efficiency, runtime, and support boarder scope of designs.
A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience.
Familiarity with ASIC power analysis and optimization
Familiarity with machine learning algorithms and programming
Familiarity with Verilog and System Verilog.
Familiarity with SOC design flow and methodology
Familiarity with scripting in Python.
Familiarity computer architecture, logic and circuits design
Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups

Nice-to-haves

Familiarity signal processing is a plus
Silicon power measurement experience is a plus
SOC power modeling, low power design and power optimization experience is a plus

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

llmmachine learningpython

Platform: apple
Effort: medium