Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: The candidate will join a highly visible and influential team of high-speed physical interface (PHY) and mixed signal IP experts tasked with integration and support of 3 rd Party Memory/Serdes PHY and mixed signal IP across all AMD products. The team works across a large swath of AMD integration and post-silicon teams as well as with IP vendors and AMD customers. THE PERSON: The ideal candidate is self-motivated to work independently as well as collaboratively with technical people across a variety of AMD and vendor/partner teams, and who thinks of herself/himself as a problem solver. RESPONSIBILITIES: • Serve as the AMD technical owner for selected third-party Memory/Serdes PHY and mixed-signal IP across multiple product programs. • Provide technical leadership for the IP/PHY throughout the product lifecycle, from architecture --> integration --> post-silicon validation --> production. • Collaborate directly with third-party IP vendors to support IP evaluation, design transfer, release collateral, and integration into AMD SoCs; working closely with the Technical Project Manager. • Partner with SoC integration teams to ensure electrical, logical, and physical quality of IP integration. • Drive system-level architectural decisions by balancing performance, power, area, cost, and implementation constraints. • Interpret industry standards and customer requirements, translating them into silicon, package, PCB, and validation specifications. • Support package and PCB design teams with signal integrity and power integrity analysis, debug, and optimization; Partnering with SI/PI experts within AMD. • Evaluate new PHY and mixed-signal IP technologies for licensing and adoption. • Partner with post-silicon validation teams in directing first-silicon bring-up, debug, characterization, compliance testing, ATE production test support, and customer issue resolution. • Analyze post-silicon results and drive improvements to future PHY architectures, design methodologies, and IP development processes. • Provide technical guidance across the hardware development lifecycle, leveraging understanding of transistor-level design, system architecture, and SoC integration. PREFERRED EXPERIENCE: • Strong experience designing high-speed mixed-signal IP, ideally with system-level architecture experience. Should have breadth of knowledge across the full IP hardware development process (or strong interest in developing it) and experience with integration IP into an SOC • Design knowledge of high-speed I/O SerDes or Memory PHY architectures and blocks, plus general mixed-signal IP, e.g. CTLE, FFE, DFE, VGA, CDR, PLL/DLL, TX driver, EMC, GPIO, etc. • Experience with one or more interface protocols like HBM, LPDDR, DDR, GDDR, PCIe, Ethernet, USB, DisplayPort, HDMI, MIPI etc. is preferred. • Experience with advanced FinFET semiconductor technologies at and below 7nm. • Basic understanding of RTL, logic design, and digital circuits • Python and/or Perl programming desirable. Should be familiar with UNIX environment. • Laboratory experience, including hands-on use of equipment: BERT, oscilloscope, logic analyzer, etc. desirable. • Strong analytical/problem solving skills, ability to learn quickly, and attention to detail. • Good teamwork and oral and written communications skills are critical. ACADEMIC CREDENTIALS: • B.S. or M.S. Electrical Engineering preferred LOCATION: Austin, TX (open to other AMD Locations.) This role is not eligible for visa sponsorship. #LI-DP1 Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Requirements

Must-haves

ADVANCE YOUR CAREER. ADVANCE THE WORLD.
The ideal candidate is self-motivated to work independently as well as collaboratively with technical people across a variety of AMD and vendor/partner teams, and who thinks of herself/himself as a problem solver.
Serve as the AMD technical owner for selected third-party Memory/Serdes PHY and mixed-signal IP across multiple product programs.
Provide technical leadership for the IP/PHY throughout the product lifecycle, from architecture --> integration --> post-silicon validation --> production.
Collaborate directly with third-party IP vendors to support IP evaluation, design transfer, release collateral, and integration into AMD SoCs; working closely with the Technical Project Manager.
Partner with SoC integration teams to ensure electrical, logical, and physical quality of IP integration.
Drive system-level architectural decisions by balancing performance, power, area, cost, and implementation constraints.
Interpret industry standards and customer requirements, translating them into silicon, package, PCB, and validation specifications.
Support package and PCB design teams with signal integrity and power integrity analysis, debug, and optimization; Partnering with SI/PI experts within AMD.
Evaluate new PHY and mixed-signal IP technologies for licensing and adoption.
Partner with post-silicon validation teams in directing first-silicon bring-up, debug, characterization, compliance testing, ATE production test support, and customer issue resolution.
Analyze post-silicon results and drive improvements to future PHY architectures, design methodologies, and IP development processes.
Provide technical guidance across the hardware development lifecycle, leveraging understanding of transistor-level design, system architecture, and SoC integration.
LOCATION: Austin, TX (open to other AMD Locations.)
Benefits offered are described: AMD benefits at a glance .

Nice-to-haves

Design knowledge of high-speed I/O SerDes or Memory PHY architectures and blocks, plus general mixed-signal IP, e.g. CTLE, FFE, DFE, VGA, CDR, PLL/DLL, TX driver, EMC, GPIO, etc.
Experience with one or more interface protocols like HBM, LPDDR, DDR, GDDR, PCIe, Ethernet, USB, DisplayPort, HDMI, MIPI etc. is preferred.
Experience with advanced FinFET semiconductor technologies at and below 7nm.
Basic understanding of RTL, logic design, and digital circuits
Python and/or Perl programming desirable. Should be familiar with UNIX environment.
Laboratory experience, including hands-on use of equipment: BERT, oscilloscope, logic analyzer, etc. desirable.
Strong analytical/problem solving skills, ability to learn quickly, and attention to detail.
Good teamwork and oral and written communications skills are critical.
B.S. or M.S. Electrical Engineering preferred

Application prep

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Keywords to mirror

aipython

Platform: amd
Effort: medium