Job description

Principal Engineer, Electrical Link Architecture Location: San Jose, CA (on-site) Ayar Labs is solving the I/O bandwidth bottlenecks inherent in modern AI compute architectures. As pioneers of co-packaged optics (CPO), we develop silicon photonics solutions that deliver unprecedented bandwidth density and reach, at a fraction of the power consumption required to scale next-generation AI models. Backed by industry giants like NVIDIA, AMD, Mediatek, and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. The Link Design and Architecture team is responsible for the performance and robustness of every optical link Ayar Labs ships, from component models through architecture, link analysis, specification, and yield. As a Principal Engineer in Electrical Link Architecture, you own the electrical path end to end: the analog front ends on both sides of the optics, the equalization and clocking that close the link, and the models that prove it works before silicon exists. You decide how the link budget is split across blocks and between analog front end and DSP, set the block specs the PHY team delivers to, and reconcile silicon against the model when it comes back. The work is as much forward looking as it is advancing the current state of the art: what the next generations of the link look like as lane rates climb, where the power goes, and which architectures are worth taping out. You should be able to look at the analog front end and the DSP as one system, understand how they work together to close the link, and turn that into clear requirements for the AMS and ASIC teams. Essential functions • Own the end-to-end electrical architecture of the optical link (driver through modulator, photodetector through TIA, analog front end, equalization, clock recovery) and the electrical link budget that goes with it. • Decide how equalization and gain are partitioned between the analog front end and DSP, with power, area, and margin as explicit tradeoffs, and own that decision through tapeout. • Translate link requirements into block-level electrical specs (bandwidth, noise, linearity, jitter, offset, swing) for the AMS design team, and sign off that the blocks as designed close the link at yield. • Build the electrical models that matter: compact models of the analog front end and DSP chain at BER and link-margin fidelity, and Verilog-A models of the electrical/optical interface co-designed with AMS and photonics. • Lead silicon correlation for the electrical path with validation and SerDes characterization; drive the model or the design to change when they disagree. • Run statistical link analysis (corners, Monte Carlo, yield) in the team's in-house simulation stack; flag product specs that cannot be met and lay out the options. • Own the exploration of next-generation electrical link architectures (data rate per lane, modulation format, DSP-light versus ADC-based receivers, new electrical/optical interfaces) and turn them into concrete tapeout recommendations and roadmap input. • Represent the electrical link architecture in cross-functional reviews, customer engagements, and foundry/EDA partner discussions; mentor the team on analog front-end behavior. Required Qualifications • BS in Electrical Engineering, Physics, or a related field. • 8+ years in high-speed wireline or optical link design, spanning both the analog front end and the equalization that closes the link. • Hands-on design, or direct co-design, of analog front-end blocks (TIA, CTLE, VGA, sampler, TX driver, clocking) in a high-speed SerDes or optical transceiver, with a deep understanding of how their bandwidth, noise, linearity, offset, and jitter shape the link, reasoned from a schematic and a Spectre result rather than a behavioral model. • Strong command of equalization and clock recovery (CTLE, FFE, DFE, MLSE, ADC-based receivers, adaptation, CDR), including how to partition it between analog and DSP and how front-end non-idealities limit what DSP can recover. • Proficiency in Verilog-A and mixed-signal simulation; working fluency in Cadence Virtuoso / ADE / Spectre. • Statistical circuit and link analysis (corners, Monte Carlo, BER and margin prediction) and strong Python for scientific computing. Preferred Qualifications • MS or PhD in Electrical Engineering, Physics, or a related field. • Architected a SerDes or optical PHY from concept to production silicon, including first-silicon debug. • Direct experience with optical link electronics: TIAs, high-swing modulator drivers, microring modulators and thermal control loops, laser RIN and extinction-ratio budgeting. • PAM4 and analog/DSP partitioning at 100 Gb/s per lane and above. • Familiarity with chiplet / die-to-die interfaces (UCIe), optical transceiver standards (OIF CEI, IEEE 802.3), and shared link-simulation codebases. Salary Range: $224,000 - $262,000 NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers. Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

Requirements

Must-haves

Principal Engineer, Electrical Link Architecture
Location: San Jose, CA (on-site)
Own the end-to-end electrical architecture of the optical link (driver through modulator, photodetector through TIA, analog front end, equalization, clock recovery) and the electrical link budget that goes with it.
Decide how equalization and gain are partitioned between the analog front end and DSP, with power, area, and margin as explicit tradeoffs, and own that decision through tapeout.
Translate link requirements into block-level electrical specs (bandwidth, noise, linearity, jitter, offset, swing) for the AMS design team, and sign off that the blocks as designed close the link at yield.
Build the electrical models that matter: compact models of the analog front end and DSP chain at BER and link-margin fidelity, and Verilog-A models of the electrical/optical interface co-designed with AMS and photonics.
Lead silicon correlation for the electrical path with validation and SerDes characterization; drive the model or the design to change when they disagree.
Run statistical link analysis (corners, Monte Carlo, yield) in the team's in-house simulation stack; flag product specs that cannot be met and lay out the options.
Represent the electrical link architecture in cross-functional reviews, customer engagements, and foundry/EDA partner discussions; mentor the team on analog front-end behavior.
BS in Electrical Engineering, Physics, or a related field.
8+ years in high-speed wireline or optical link design, spanning both the analog front end and the equalization that closes the link.
Proficiency in Verilog-A and mixed-signal simulation; working fluency in Cadence Virtuoso / ADE / Spectre.
Statistical circuit and link analysis (corners, Monte Carlo, BER and margin prediction) and strong Python for scientific computing.

Nice-to-haves

MS or PhD in Electrical Engineering, Physics, or a related field.
Architected a SerDes or optical PHY from concept to production silicon, including first-silicon debug.
Direct experience with optical link electronics: TIAs, high-swing modulator drivers, microring modulators and thermal control loops, laser RIN and extinction-ratio budgeting.
PAM4 and analog/DSP partitioning at 100 Gb/s per lane and above.
Familiarity with chiplet / die-to-die interfaces (UCIe), optical transceiver standards (OIF CEI, IEEE 802.3), and shared link-simulation codebases.

Application prep

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aipython

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