Job description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering. Job Responsibilities Architect and design memory subsystems Implement RTL of subsystem designs Place and route (physical design) Design closure: timing, DRC, LVS, EM/IR, etc. Gate netlist synthesis Skill Set Required Strong design skills Ability to write and debug Verilog RTL code Place and route expertise Proficient in running STA, DRC, EM/IR tools, and attaining design closure Ability to code in Python Good understanding of synthesis tools and running synthesis Capable of running and debugging logical equivalency checkers Familiar with memory behavior Proficient in writing automation scripts, and tools savvy Good communication, interpersonal, and leadership skills Motivated, self-driven, and good at multitasking Compensation and Benefits The annual base salary range for this position is USD 109,700.00 To USD 175,500.00 As a valued member of our team, you ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company s growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Requirements

Must-haves

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Architect and design memory subsystems
Implement RTL of subsystem designs
Place and route (physical design)
Design closure: timing, DRC, LVS, EM/IR, etc.
Gate netlist synthesis
Skill Set Required
Strong design skills
Ability to write and debug Verilog RTL code
Place and route expertise
Proficient in running STA, DRC, EM/IR tools, and attaining design closure
Ability to code in Python
Good understanding of synthesis tools and running synthesis
Capable of running and debugging logical equivalency checkers
Familiar with memory behavior
Proficient in writing automation scripts, and tools savvy
Good communication, interpersonal, and leadership skills
Motivated, self-driven, and good at multitasking

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)