Job description

Title: Senior ASIC Physical Design Engineer Location: San Jose, CA (100% Onsite) Location for the role is on-site at San Jose, 5-days a week Type: FTE Permanent role Job Description: Client is searching for a Physical Design Engineer to join the ASIC Products Division. This position involves working with the latest technology to continue driving next generation AI designs. This position will require in-depth knowledge and expertise in Physical Design aspects of taking Netlist to silicon tape-out. Responsibilities include, but are not limited to the following: Execution of Physical Design, Physical Verification, and Timing Closure Timing closure through various methods and strategies; preferable in-depth experience in top-level STA EM/IR Analysis, Place and Route Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques Floor-planning and Layout; preferable in-depth experience in top-level floorplanning Flow and Methodology Development Collaborating with IC Design RTL Engineers Required attributes: TCL/PERL Scripting Proficiency in related EDA Tools Full physical design cycle experience: RTL to Tape-out Excellent verbal and written communication skills Education and Experience Requirements: Minimum: Bachelor’s degree required in Electrical Engineering or Electronics Engineering 8+ Years of relevant experience

Requirements

Must-haves

Title: Senior ASIC Physical Design Engineer
Location: San Jose, CA (100% Onsite)
Location for the role is on-site at San Jose, 5-days a week
Type: FTE Permanent role
Responsibilities include, but are not limited to the following:
Execution of Physical Design, Physical Verification, and Timing Closure
Timing closure through various methods and strategies; preferable in-depth experience in top-level STA
EM/IR Analysis, Place and Route
Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques
Floor-planning and Layout; preferable in-depth experience in top-level floorplanning
Flow and Methodology Development
Collaborating with IC Design RTL Engineers
TCL/PERL Scripting
Proficiency in related EDA Tools
Full physical design cycle experience: RTL to Tape-out
Excellent verbal and written communication skills
Minimum: Bachelor’s degree required in Electrical Engineering or Electronics Engineering
8+ Years of relevant experience

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Platform: catsone
Effort: medium

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