Job description

Be visionary Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research. We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins. Job Description Job Summary: We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These chips form the heart of our infrared detectors, sensors, and cameras—used in applications ranging from firefighting and security to scientific research and government contracts. As part of our close-knit team, you will play a key role in producing analog and mixed-signal circuit layouts by preparing multi-dimensional, detailed drawings of the semiconductor devices from schematics provided by design engineering. You will collaborate closely with analog and digital circuit designers, ensuring precision in signal integrity, parasitic coupling, and matched transistor pairs. From initial design discussions to final tape-out, your expertise will help shape industry-leading imaging technology. Must be US Citizen or PERM Resident Primary Duties & Responsibilities: Develop high-quality analog/mixed-signal IC layouts and create GDS databases of completed designs using Cadence and Siemens software tools. Collaborate with circuit designers to optimize floor-planning, placement, and routing. Ensure layout integrity and compliance to foundry wafer fabrication with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Parasitic Extraction (PEX), and the use of Process Design Kits (PDK). Interface with ROIC designers, detector engineers, systems engineers, processors, test, and packaging teams to optimize performance, manufacturability and yield. Present weekly updates to project schedule and percent task completions. Prepare reports for design reviews and internal and external customer presentations. Perform proper handling of Export Controlled Information and exercise discipline in following GTC protocol and jurisdictional classification. Release and maintain design documents per the ISO quality system requirements. What You Bring: Bachelor’s degree in engineering or related field with 10 years of industry experience Expertise in analog/mixed-signal layout design for CMOS circuits, ideally in 180nm, 130nm, or 75nm process nodes Proficiency in Cadence Virtuoso XL for connectivity-aware design Strong understanding of Calibre verification (DRC, LVS) and troubleshooting techniques Experience with custom cell-based layout and top-level floor planning, with work on focal-plane arrays a plus Technical knowledge of wire resistance, coupling capacitance, and best practices for minimizing parasitic effects Excellent communication skills and the ability to work effectively within a multidisciplinary team Programming/scripting skills in SKILL, TCL, Shell, or Python Salary Range: $113,600.00-$151,400.000 The anticipated salary range listed for this role is only an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, local regulations (such as minimum wage), education/training, work experience, key skills, and type of position. Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders. Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions. Teledyne is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age, or any other characteristic or non-merit based factor made unlawful by federal, state, or local laws.

Requirements

Must-haves

Be visionary
We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.
Must be US Citizen or PERM Resident
Develop high-quality analog/mixed-signal IC layouts and create GDS databases of completed designs using Cadence and Siemens software tools.
Collaborate with circuit designers to optimize floor-planning, placement, and routing.
Ensure layout integrity and compliance to foundry wafer fabrication with Design Rule Checks (DRC), Layout Versus Schematic (LVS), Parasitic Extraction (PEX), and the use of Process Design Kits (PDK).
Interface with ROIC designers, detector engineers, systems engineers, processors, test, and packaging teams to optimize performance, manufacturability and yield.
Present weekly updates to project schedule and percent task completions. Prepare reports for design reviews and internal and external customer presentations.
Perform proper handling of Export Controlled Information and exercise discipline in following GTC protocol and jurisdictional classification.
Release and maintain design documents per the ISO quality system requirements.
Bachelor’s degree in engineering or related field with 10 years of industry experience
Expertise in analog/mixed-signal layout design for CMOS circuits, ideally in 180nm, 130nm, or 75nm process nodes
Proficiency in Cadence Virtuoso XL for connectivity-aware design
Strong understanding of Calibre verification (DRC, LVS) and troubleshooting techniques
Technical knowledge of wire resistance, coupling capacitance, and best practices for minimizing parasitic effects
Excellent communication skills and the ability to work effectively within a multidisciplinary team
Programming/scripting skills in SKILL, TCL, Shell, or Python
$113,600.00-$151,400.000

Nice-to-haves

Experience with custom cell-based layout and top-level floor planning, with work on focal-plane arrays a plus

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Vision