Job description

Role: Hardware Design Engineer Location: Santa Clara, CA (Onsite) Pay Rate: $80 - $92/hr on W2 12 Months Contract The Role This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities. The Person •Strong analytical and problem solving skills with a pronounced attention to detail •Strong communication, mentoring and leadership skills •Self-driven, Methodical and attention to detail in troubleshooting and problem-solving •Can work well with cross functional teams •Excellent verbal and written communication skills Responsibility •Design, develop, and implement complex FPGA architectures using Xilinx devices (UltraScale, UltraScale+, Versal, etc.) •Create RTL designs using Verilog/SystemVerilog for high-performance applications •Perform FPGA prototype design, implementation, and bring-up activities •Create comprehensive design documentation, specifications, and technical reports •Perform timing analysis, closure, and optimization using Vivado tools •Conduct board-level bring-up and system integration testing •Debug complex hardware/firmware issues using logic analyzers, oscilloscopes, and other test equipment •Validate FPGA designs against specifications and performance requirements •Independently troubleshoot and resolve challenging technical issues •Work closely with hardware, software, and systems engineering teams •Participate in design reviews and technical discussions •Communicate project status, risks, and technical challenges to stakeholders Preferred Skill Set & Experience •Extensive experience in field of FPGA hardware prototyping •Have worked with the prototyping platforms such as Xilinx reference boards, Synopsys HAPS platforms etc •Experience with Xilinx Versal ACAP or UltraScale+ devices •Knowledge of FPGA synthesis tools and methodologies •Familiarity with Python/TCL scripting for design automation •Knowledge of FPGA-based system architecture and hardware/software co-design •Familiarity with board design and hardware debugging tools (logic analyzers, oscilloscopes, protocol analyzers) •Fluent in System Verilog and a familiarity with simulation and debug •Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus EDUCATION: •BS ( or higher ) degree in Electrical or Computer Engineering desired

Requirements

Must-haves

Role: Hardware Design Engineer
Location: Santa Clara, CA (Onsite)
Pay Rate: $80 - $92/hr on W2
12 Months Contract
•Strong analytical and problem solving skills with a pronounced attention to detail
•Strong communication, mentoring and leadership skills
•Self-driven, Methodical and attention to detail in troubleshooting and problem-solving
•Can work well with cross functional teams
•Excellent verbal and written communication skills
Responsibility
•Design, develop, and implement complex FPGA architectures using Xilinx devices (UltraScale, UltraScale+, Versal, etc.)
•Create RTL designs using Verilog/SystemVerilog for high-performance applications
•Perform FPGA prototype design, implementation, and bring-up activities
•Create comprehensive design documentation, specifications, and technical reports
•Perform timing analysis, closure, and optimization using Vivado tools
•Conduct board-level bring-up and system integration testing
•Debug complex hardware/firmware issues using logic analyzers, oscilloscopes, and other test equipment
•Validate FPGA designs against specifications and performance requirements
•Independently troubleshoot and resolve challenging technical issues
•Work closely with hardware, software, and systems engineering teams
•Participate in design reviews and technical discussions
•Communicate project status, risks, and technical challenges to stakeholders

Nice-to-haves

Preferred Skill Set & Experience
•Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus

Application prep

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python

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