Job description

Job Details: Job Description: Position Summary Altera is seeking a Product Architecture Model Development Leader to drive the creation, quality, and evolution of behavioral and architectural models that represent next-generation FPGA silicon before and during RTL development. This role sits at the intersection of architecture, verification, software enablement, and customer enablement — the behavioral models you and your team build become the single source of truth used by architects for pathfinding and performance analysis, by verification teams for golden-reference checking, by RTL design teams as an internal product reference for intended behavior, and by software/compiler teams for early enablement, long before silicon or even RTL exists. These models will also enable customers earlier in the product lifecycle through pre-silicon functional simulation, early RTL and data-flow development, and software and driver development ahead of device availability. You will lead a team of model developers and set the technical direction for how Altera represents FPGA fabric, hard IP, and system-level behavior in executable, simulatable form. Key Responsibilities Technical Leadership Lead a team of behavioral modeling engineers responsible for developing cycle-approximate and functional models of FPGA architecture (fabric, DSP blocks, memory hierarchies, hard IP, transceivers, NoC, etc.) Define modeling methodology, coding standards, and architecture for behavioral models (C , SystemC, Python) used across the pre-silicon design flow Own the roadmap for model development in lockstep with architecture definition milestones — from early concept and pathfinding through RTL freeze Drive model accuracy, performance, and maintainability trade-offs, ensuring models scale across increasingly complex FPGA generations Cross-Functional Model Ownership Partner with silicon architects to translate architectural specifications and microarchitecture decisions into executable behavioral models Establish the architectural model as a trusted internal product reference for intended system behavior, functional flows, interfaces, and architectural rules across architecture, design, verification, firmware, and software teams Collaborate with verification teams to ensure behavioral models serve as golden references / scoreboards for RTL verification (UVM environments, formal checking, co-simulation) Work with performance modeling and pathfinding teams to support design-space exploration, power/performance/area (PPA) trade-off studies, and early customer workload analysis Drive early customer enablement by delivering models that support pre-silicon prototyping, functional simulation, RTL and data-flow development, and evaluation of product capabilities before silicon availability Support software, firmware, compiler, driver, and tools teams that depend on behavioral models for early development, platform bring-up, and functional simulation ahead of silicon availability Work with Quartus and customer-facing engineering teams to evolve models into early product representations that allow customers and FAEs to begin development sooner and reduce time to first successful design on new devices Interface with RTL design teams to resolve model-vs-RTL discrepancies and maintain model/RTL equivalence throughout the design cycle Process and Infrastructure Establish and maintain simulation infrastructure, regression frameworks, and CI pipelines for model validation Drive model versioning, documentation, and configuration management practices so models remain a trusted reference across multiple concurrent projects/generations Champion automation to reduce hand-off latency between architecture spec, model, RTL, and verification Identify opportunities to leverage or build tooling (e.g., model generators, spec-to-model flows) that improve modeling velocity and reduce spec ambiguity People Leadership Hire, mentor, and grow a team of behavioral/architecture modeling engineers Set individual and team goals aligned with architecture program milestones Foster close working relationships between the modeling team and adjacent architecture, verification, and design organizations Core Competencies Strong architectural and systems-level thinking — able to reason about hardware behavior at multiple levels of abstraction Rigor and precision in translating ambiguous specs into unambiguous, testable model behavior Leadership style that balances deep technical involvement with team development and delegation Ability to manage competing priorities across multiple concurrent silicon programs Strong collaborator across architecture, verification, RTL design, and software organizations Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $231,500 - $341,075 USD We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations. #LI-M D1 Qualifications: Minimum Qualifications: Bachelor s degree in Computer Engineering, Electrical Engineering, Computer Science, or related field (Master s or PhD preferred) 15 years of experience in silicon architecture, design, or verification, with 5 years in a technical leadership role Strong hands-on experience developing behavioral, functional, or performance models in C , SystemC, and/or System Verilog Deep understanding of FPGA or ASIC architecture fundamentals (fabric architecture, memory subsystems, interconnect, hard IP blocks) Experience bridging architecture specifications into simulatable models used for verification and/or performance analysis Experience using pre-silicon models to enable software, firmware, drivers, or customer development ahead of RTL or silicon availability Familiarity with RTL design and verification flows (SystemVerilog/UVM) sufficient to reason about model-RTL equivalence Track record of leading technical teams delivering complex infrastructure/models on multi-quarter silicon program timelines Strong communication skills — able to represent modeling team priorities to architecture leadership and coordinate across verification, design, and software orgs Preferred Qualifications: Prior experience specifically with FPGA architecture ( embedded memory, transceivers, NoC/interconnect) Experience with performance/pathfinding modeling for PPA trade-off studies Experience building or maintaining spec-to-model or model-to-RTL automation/codegen flows Familiarity with formal methods or golden-model-based verification methodologies Experience supporting early software/compiler enablement using pre-silicon models Experience delivering customer-consumable pre-silicon models or integrating architectural models into FPGA/ASIC development tools for early customer prototyping Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Requirements

Must-haves

Job Description: Position Summary
You will lead a team of model developers and set the technical direction for how Altera represents FPGA fabric, hard IP, and system-level behavior in executable, simulatable form.
Technical Leadership
Lead a team of behavioral modeling engineers responsible for developing cycle-approximate and functional models of FPGA architecture (fabric, DSP blocks, memory hierarchies, hard IP, transceivers, NoC, etc.)
Define modeling methodology, coding standards, and architecture for behavioral models (C , SystemC, Python) used across the pre-silicon design flow
Own the roadmap for model development in lockstep with architecture definition milestones — from early concept and pathfinding through RTL freeze
Drive model accuracy, performance, and maintainability trade-offs, ensuring models scale across increasingly complex FPGA generations
Cross-Functional Model Ownership
Partner with silicon architects to translate architectural specifications and microarchitecture decisions into executable behavioral models
Collaborate with verification teams to ensure behavioral models serve as golden references / scoreboards for RTL verification (UVM environments, formal checking, co-simulation)
Work with performance modeling and pathfinding teams to support design-space exploration, power/performance/area (PPA) trade-off studies, and early customer workload analysis
Drive early customer enablement by delivering models that support pre-silicon prototyping, functional simulation, RTL and data-flow development, and evaluation of product capabilities before silicon availability
Support software, firmware, compiler, driver, and tools teams that depend on behavioral models for early development, platform bring-up, and functional simulation ahead of silicon availability
Interface with RTL design teams to resolve model-vs-RTL discrepancies and maintain model/RTL equivalence throughout the design cycle

Nice-to-haves

Bachelor s degree in Computer Engineering, Electrical Engineering, Computer Science, or related field (Master s or PhD preferred)
Prior experience specifically with FPGA architecture ( embedded memory, transceivers, NoC/interconnect)
Experience with performance/pathfinding modeling for PPA trade-off studies
Experience building or maintaining spec-to-model or model-to-RTL automation/codegen flows
Familiarity with formal methods or golden-model-based verification methodologies
Experience supporting early software/compiler enablement using pre-silicon models
Experience delivering customer-consumable pre-silicon models or integrating architectural models into FPGA/ASIC development tools for early customer prototyping
Job Type: Regular
Shift: Shift 1 (United States of America)
Primary Location: San Jose, California, United States

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: workday
Effort: long