Job description

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm is seeking an experienced Hardware Scale-Out Architect to help define the next generation of AI datacenter products. This role is responsible for architecting large-scale Ethernet-based AI/datacenter fabrics that connect servers, accelerators, racks, and multi-rack clusters. The ideal candidate will bring deep expertise across Ethernet, UEC, RoCE/RDMA, NICs/SuperNICs, scale-out switches, scale-up interconnects, and end-to-end system data movement. The selected candidate will drive system architecture and requirements from the accelerator card and server level through rack and cluster-scale deployments, partnering closely with SoC, software, card, platform, and product teams. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. Responsibilities: • Define next-generation scale-out network architectures for AI and cloud datacenter deployments. • Develop end-to-end system architecture spanning accelerator cards, servers, racks, and multi-rack clusters. • Drive architecture and requirements for Ethernet fabrics, NICs/SuperNICs, switch ASICs, transport protocols, in-network collectives, telemetry, security, virtualization, RAS, and reliability features. • Analyze DMA engines, data flows, packet flows, and system bottlenecks to optimize bandwidth, latency, utilization, and scalability. • Collaborate with software, SoC design, card design, platform, and validation teams to realize connectivity solutions for AI scale-up and scale-out deployments. • Provide technical leadership across physical, link, transaction, transport, and protocol layers of high-speed interfaces and datacenter networking systems. Requirements: • 8+ years of hardware architecture, design, validation, testing, or commercialization experience in datacenter, networking, accelerator, or high-speed I/O products. • Strong understanding of Ethernet, InfiniBand, RoCEv2, RDMA, and related transport protocols. • Ability to work closely with software teams to optimize end-to-end data movement for high bandwidth, low latency, and efficient resource utilization. • 3+ years of experience with datacenter products such as servers, accelerators, NICs, switches, racks, or cluster-scale systems. • Strong knowledge of scale-out networking and scale-up interconnect architectures for AI and cloud infrastructure. • In-depth knowledge of Ethernet, high-speed SerDes, PCIe/CXL-class interfaces, and board/system-level connectivity tradeoffs. • Strong understanding of telemetry, observability, RAS, reliability, error handling, and failure-mode analysis in large-scale systems. • Strong understanding of security, isolation, virtualization, and multi-tenant deployment requirements in datacenter environments. • Strong understanding of DMA engines, memory hierarchy, I/O virtualization, and accelerator data-movement architectures. • Ability to operate effectively in a high-caliber, cross-functional, international, and multi-site engineering environment. Preferred Skills and Experience: • Good understanding of PCIe, CXL, and UCIe protocols and their use in accelerator, server, and rack-scale architectures. • Familiarity with Ethernet switch management and control-plane ecosystems such as SONiC, SAI, OpenBMC, Linux networking, and related platform software. • Good understanding of high-speed SerDes and Ethernet PHY design considerations, including signal integrity, reach, power, latency, and platform tradeoffs. • Ability to work with customers, product management, architecture, and engineering teams to gather requirements and translate them into clear technical specifications. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits : $221,100.00 - $331,700.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link . If you would like more information about this role, please contact Qualcomm Careers .

Requirements

Must-haves

Qualcomm Technologies, Inc.
Engineering Group, Engineering Group > ASICS Engineering
Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Define next-generation scale-out network architectures for AI and cloud datacenter deployments.
Develop end-to-end system architecture spanning accelerator cards, servers, racks, and multi-rack clusters.
Drive architecture and requirements for Ethernet fabrics, NICs/SuperNICs, switch ASICs, transport protocols, in-network collectives, telemetry, security, virtualization, RAS, and reliability features.
Analyze DMA engines, data flows, packet flows, and system bottlenecks to optimize bandwidth, latency, utilization, and scalability.
Collaborate with software, SoC design, card design, platform, and validation teams to realize connectivity solutions for AI scale-up and scale-out deployments.
Provide technical leadership across physical, link, transaction, transport, and protocol layers of high-speed interfaces and datacenter networking systems.
8+ years of hardware architecture, design, validation, testing, or commercialization experience in datacenter, networking, accelerator, or high-speed I/O products.
Strong understanding of Ethernet, InfiniBand, RoCEv2, RDMA, and related transport protocols.
Ability to work closely with software teams to optimize end-to-end data movement for high bandwidth, low latency, and efficient resource utilization.
3+ years of experience with datacenter products such as servers, accelerators, NICs, switches, racks, or cluster-scale systems.
Strong knowledge of scale-out networking and scale-up interconnect architectures for AI and cloud infrastructure.
In-depth knowledge of Ethernet, high-speed SerDes, PCIe/CXL-class interfaces, and board/system-level connectivity tradeoffs.
Strong understanding of telemetry, observability, RAS, reliability, error handling, and failure-mode analysis in large-scale systems.
Strong understanding of security, isolation, virtualization, and multi-tenant deployment requirements in datacenter environments.
Strong understanding of DMA engines, memory hierarchy, I/O virtualization, and accelerator data-movement architectures.
Ability to operate effectively in a high-caliber, cross-functional, international, and multi-site engineering environment.
Good understanding of PCIe, CXL, and UCIe protocols and their use in accelerator, server, and rack-scale architectures.
Familiarity with Ethernet switch management and control-plane ecosystems such as SONiC, SAI, OpenBMC, Linux networking, and related platform software.
Good understanding of high-speed SerDes and Ethernet PHY design considerations, including signal integrity, reach, power, latency, and platform tradeoffs.

Nice-to-haves

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