Job description

Position : Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Pay Rate : 70/hr on W2 Client : Tesla JD for PD: • Exposure to TSMC 2NP/3NP is must • Perform endtoend physical design flow: • Floorplanning • Power planning (PG grid, IR) • Placement & optimization • CTS (Clock Tree Synthesis) • Routing • Postroute optimization • Achieve timing closure across all modes and corners • Resolve DRC, LVS, ERC and signoff violations • Handle lowpower design techniques: • MultiVt, Multivoltage (UPF) • Power gating, clock gating • Perform physical verification and signoff: • STA (Primetime) • SI / Crosstalk • IR drop & EM analysis • Work on advanced nodes (7nm, 5nm, 3nm or below) • Collaborate with: • RTL & Microarchitecture teams • DFT & Test engineers • Foundry and CAD teams • Debug complex timing, congestion, power, and variability issues • Drive methodology improvements and automation (scripts/flows) Notes :- All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits : Danta offers a compensation package to all W2 employees that are competitive in the industry. It consists of competitive pay, the option to elect healthcare insurance (Dental, Medical, Vision), Major holidays and Paid sick leave as per state law. The rate/ Salary range is dependent on numerous factors including Qualification, Experience and Location.

Requirements

Must-haves

Position : Physical Design Engineer
Location : Palo Alto, CA (Full Onsite)
Pay Rate : 70/hr on W2
Client : Tesla
Exposure to TSMC 2NP/3NP is must
Floorplanning
Power planning (PG grid, IR)
Placement & optimization
CTS (Clock Tree Synthesis)
Postroute optimization
Achieve timing closure across all modes and corners
Resolve DRC, LVS, ERC and signoff violations
MultiVt, Multivoltage (UPF)
Power gating, clock gating
STA (Primetime)
SI / Crosstalk
IR drop & EM analysis
Work on advanced nodes (7nm, 5nm, 3nm or below)
RTL & Microarchitecture teams
DFT & Test engineers
Foundry and CAD teams
Debug complex timing, congestion, power, and variability issues
Drive methodology improvements and automation (scripts/flows)

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

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Effort: medium

Benefits

Benefits detected in the listing.

Dental

Vision