Principal FPGA Networking Engineer at Trident Systems

Job description

Position Title: Principal FPGA Networking Engineer Requisition ID: 1874 Position Location: Remote Position Reports To: Senior Manager, FPGA Engineering Supervises Others: No At Trident Systems Space Electronic Systems (SES) division, we believe in the power of using strong engineering principles to drive innovation and solve complex problems. We foster a culture of rigorous engineering and continuous improvement, leveraging the full knowledge of our organization through collaborative product development processes that include design and peer reviews. We combine our expertise in space electronics with right-sized development processes to create innovative, high-performance space-based electronic systems that meet our customers' evolving needs. We are a mission partner supporting DoD, Intelligence Community, and Civil space customers. We develop complex, radiation-effects-mitigated designs that balance competing requirements in modern space programs, delivering cutting-edge solutions that enable our customers to achieve more in space. Position Summary The Principal FPGA Networking Engineer plays a critical role in the design and development of advanced FPGA-based networking solutions supporting space-based electronic systems. This position is responsible for architecting, implementing, and verifying complex, high-speed programmable logic designs for on-board networking, data transport, and packet processing functions using the latest AMD (Xilinx) technologies. The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system integration, with a strong specialization in FPGA-based networking: Ethernet (IEEE 802.3), high-speed serial interfaces, packet switching architectures, routers and switches, and hardware implementation of networking protocols (e.g., IP, TCP/UDP). They thrive in a collaborative, multi-disciplinary environment delivering mission-critical solutions to DoD, Intelligence Community, and Civil space customers. Duties and Responsibilities • Work within a multi-discipline team of engineers designing on-board networking, data transport, RF, processing, and data storage solutions for space applications utilizing AMD (Xilinx) technologies (e.g., Zynq UltraScale+ MPSoC, Zynq UltraScale+ RFSoC, Versal ACAP). • Architect FPGA-based networking pipelines including Ethernet MAC/PHY integration, packet parsing/classification, switching/forwarding, buffering, and QoS mechanisms for high-reliability space systems. • Design and implement packet switching fabrics, router/switch datapaths, control logic, and buffering/queuing schemes to support high-throughput, low-latency transport across multiple interfaces and protocols. • Create and maintain complete FPGA designs using VHDL and Vivado IP Integrator with emphasis on efficient networking data-path architecture, deterministic latency, and reliable timing closure. • Code, simulate, and verify RTL modules such as Ethernet MAC/PHY interfaces (IEEE 802.3), packet processing blocks, switching/routing/queuing logic, and control interfaces to peripherals and system controllers. • Design and implement solutions that use embedded ARM processors, DDR4 memory, and high-speed serial interfaces (e.g., Aurora, PCIe, multi-rate Ethernet) to ensure robust data movement within and between FPGA-based subsystems. • Implement and optimize hardware support for networking protocols and stacks (e.g., IP, TCP/UDP, VLAN, QoS), including offload engines and checksum/segmentation logic. • Develop and maintain simulation testbenches to ensure high code coverage and verify functional correctness, robustness, and performance of networking firmware modules. • Define and maintain timing constraints and perform timing closure for multi-clock, multi-interface networking designs. • Develop and maintain IP core-level and top-level design documentation, interface control documents, and performance characterization reports (e.g., throughput, latency, packet loss, resource utilization). • Participate in code and design reviews, and contribute to FPGA design methodologies and best practices for high-performance networking and packet processing. • Collaborate closely with hardware and software engineers to integrate FPGA networking designs with system hardware, drivers, and higher-level networking stacks. • Support board bring-up and system verification in an electronic lab environment, including link bring-up, traffic generation, protocol compliance testing, network performance evaluation, and system-level debug using FPGA ILA-based tools (Vivado HW Debugger, Chipscope, SmartDebug). • Mentor junior engineers in FPGA networking architecture, protocol implementation, buffering/queuing strategies, and verification best practices. Required Qualifications • Bachelor’s degree in Computer Engineering, Electrical Engineering or related technical degree • 9+ years of related experience with a bachelor’s degree OR a 7+ years of experience with a master’s degree • Hands-on experience with FPGA-based networking design, including Ethernet (IEEE 802.3), high-speed serial links, and packet-switched architectures. • Experience implementing or integrating networking protocols and functions in hardware (e.g., IP, TCP/UDP, VLAN, QoS, router/switch datapaths, routing look-up tables). • Experience with firmware/RTL design, simulation, and verification for complex, high-throughput FPGA systems. • Experience with RTL logic design and coding using VHDL and/or Verilog. • Thorough understanding of FPGA design methodology including physical synthesis, static timing analysis, place/route, verification, power analysis, and timing closure techniques. • Experience writing simulation testbenches to identify bugs and verify designs. Preferred Qualifications • Deep understanding of data networking architectures, routers, switches, and network management concepts. • Experience with high-speed Ethernet interfaces, including 100G Ethernet, in FPGA-based designs. • Experience with multi-level security networking concepts and architectures. • Experience with network security protocols and mechanisms such as IPsec and MACsec, particularly in embedded or FPGA-based implementations. • Experience designing and verifying buffering and queuing schemes in hardware (e.g., FIFOs, circular buffers, priority queues) to support high-throughput, low-latency packet transport. • Experience with networking test and qualification, including link-level and end-to-end networking performance and protocol compliance testing. • Experience designing with AMD (Xilinx) SoC/FPGA devices using the Vivado Design Suite. • Experience using Vivado IP Integrator. • Experience designing with Microsemi (Microchip) FPGAs using Libero. • Experience using Modelsim/Questasim and/or Aldec simulation tools. • Experience using simulation verification libraries such as UVVM, UVM, OVM, etc. • Experience with board bring-up and verification in an electronic lab environment, including use of standard lab equipment (logic analyzers, oscilloscopes, signal/spectrum analyzers, Ethernet traffic generators) and FPGA ILA-based debugging tools (e.g., Vivado HW Debugger, Chipscope, SmartDebug). • Experience using revision control systems, such as Git. • Highly productive, self-motivated person able to contribute as an individual and work within a distributed team. • Experience with Linux • Experience with C/C++ Pay Information Full-Time Salary Range: $99,000 - $191,000 Please Note: Actual compensation offered will be determined based on several factors including, but not limited to, relevant experience, skills, education, certifications, internal equity, business considerations, and geographic location where applicable. Benefits Hired applicants may be eligible for benefits including but not limited to: • Health benefits • Medical • Dental • Vision • Basic life with AD&D • Short term disability • Long term disability • Ancillary (Voluntary life with AD&D, accident, critical illness, hospital, and pet) • Spending accounts (HSA, FSA, and DCFSA) • Paid time off • Holidays • 401(k) (including company match) • Tuition reimbursement • Leaves (Parental, maternity, and military) • Annual discretionary bonus (for eligible roles) Trident Systems reserves the right to change or assign other duties to this position. Trident Systems is an affirmative action and equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws. To request reasonable accommodation to participate in the job application or interview process, please contact recruiting@tridsys.com . Pay Transparency: The contractor will not discharge or in any other manner discriminate against employees or applicants because they have inquired about, discussed, or disclosed their own pay or the pay of another employee or applicant. However, employees who have access to the compensation information of other employees or applicants as a part of their essential job functions cannot disclose the pay of other employees or applicants to individuals who do not otherwise have access to compensation information, unless the disclosure is (a) in response to a formal complaint or charge, (b) in furtherance of an investigation, proceeding, hearing, or action, including an investigation conducted by the employer, or (c) consistent with the contractor’s legal duty to furnish information. 41 CFR 60-1.35(c)

Requirements

Must-haves

Position Title: Principal FPGA Networking Engineer
Requisition ID: 1874
Position Location: Remote
Position Reports To: Senior Manager, FPGA Engineering
Supervises Others: No
Duties and Responsibilities
Architect FPGA-based networking pipelines including Ethernet MAC/PHY integration, packet parsing/classification, switching/forwarding, buffering, and QoS mechanisms for high-reliability space systems.
Design and implement packet switching fabrics, router/switch datapaths, control logic, and buffering/queuing schemes to support high-throughput, low-latency transport across multiple interfaces and protocols.
Create and maintain complete FPGA designs using VHDL and Vivado IP Integrator with emphasis on efficient networking data-path architecture, deterministic latency, and reliable timing closure.
Code, simulate, and verify RTL modules such as Ethernet MAC/PHY interfaces (IEEE 802.3), packet processing blocks, switching/routing/queuing logic, and control interfaces to peripherals and system controllers.
Implement and optimize hardware support for networking protocols and stacks (e.g., IP, TCP/UDP, VLAN, QoS), including offload engines and checksum/segmentation logic.
Develop and maintain simulation testbenches to ensure high code coverage and verify functional correctness, robustness, and performance of networking firmware modules.

Nice-to-haves

Deep understanding of data networking architectures, routers, switches, and network management concepts.
Experience with high-speed Ethernet interfaces, including 100G Ethernet, in FPGA-based designs.
Experience with multi-level security networking concepts and architectures.
Experience with network security protocols and mechanisms such as IPsec and MACsec, particularly in embedded or FPGA-based implementations.
Experience designing and verifying buffering and queuing schemes in hardware (e.g., FIFOs, circular buffers, priority queues) to support high-throughput, low-latency packet transport.
Experience with networking test and qualification, including link-level and end-to-end networking performance and protocol compliance testing.
Experience designing with AMD (Xilinx) SoC/FPGA devices using the Vivado Design Suite.
Experience using Vivado IP Integrator.
Experience designing with Microsemi (Microchip) FPGAs using Libero.
Experience using Modelsim/Questasim and/or Aldec simulation tools.
Experience using simulation verification libraries such as UVVM, UVM, OVM, etc.
Experience using revision control systems, such as Git.

Application prep

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Platform: adp-workforce-now
Effort: medium

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)

Paid Time Off