Job description

About Voltai Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits. About the Team Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents. About this Role You'll define the architecture of complex SoCs and subsystems, from performance models to the specs that RTL teams build against. You'll work on real silicon programs with the world's largest semiconductor companies while shaping how Voltai's AI reasons about architecture, trade-offs, and design intent. What You’ll Do - Own architecture and microarchitecture for SoCs, subsystems, and IP blocks, from requirements through specification. - Build performance, power, and area models to drive trade-off decisions before RTL is written. - Define memory hierarchies, interconnects, and interfaces, and lead architecture reviews. - Write specifications that RTL, verification, and physical design teams can execute against. - Partner with ML researchers to teach models how expert architects reason about design trade-offs, and evaluate the architectures they propose. - Work directly with customers to translate their product requirements into silicon. What We’re Looking For - 8+ years of experience in SoC, CPU, GPU, accelerator, or networking architecture. - Track record of taking architectures from spec to tapeout. - Strong performance modeling skills (C++, SystemC, Python, or equivalent). - Deep understanding of memory systems, interconnects, cache coherence, and PPA trade-offs. - Clear technical writing and the ability to lead reviews across teams. Bonus Points - Experience with AI/ML accelerators or chiplet-based designs. - Hardware/software co-design experience. - Interest in how AI can change architecture exploration.

Requirements

Must-haves

What You’ll Do
Own architecture and microarchitecture for SoCs, subsystems, and IP blocks, from requirements through specification.
Build performance, power, and area models to drive trade-off decisions before RTL is written.
Define memory hierarchies, interconnects, and interfaces, and lead architecture reviews.
Write specifications that RTL, verification, and physical design teams can execute against.
Partner with ML researchers to teach models how expert architects reason about design trade-offs, and evaluate the architectures they propose.
Work directly with customers to translate their product requirements into silicon.
What We’re Looking For
8+ years of experience in SoC, CPU, GPU, accelerator, or networking architecture.
Track record of taking architectures from spec to tapeout.
Strong performance modeling skills (C++, SystemC, Python, or equivalent).
Deep understanding of memory systems, interconnects, cache coherence, and PPA trade-offs.
Clear technical writing and the ability to lead reviews across teams.

Nice-to-haves

Experience with AI/ML accelerators or chiplet-based designs.
Hardware/software co-design experience.
Interest in how AI can change architecture exploration.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aimlpython

Platform: ashby
Effort: quick