Job description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: The candidate would be required to work on Design Implementation activities related to place and route and/ or timing closure – floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). Should be able drive tools and methodologies to achieve desired PPA metrics. Candidate would also be required to do equivalence checks, STA, Timing closure and power optimization. Should be able to implement timing and functional ECOs. In this role, the candidate will apply Broadcom s proven design methodology and milestone flow to meet Broadcom s rigorous criteria for achieving Right-first time silicon. Primary expertise in place and route and/ or timing (constraints, STA) can be considered for this position. Requirements: Extremely proficient in design implementation activities both at block and SoC level. Well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification and/ or constraints development, constraints validation, timing analysis and closure. Experience with formal verification, timing analysis and Eco implementation. Experience with tools such as Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime etc is highly desirable. Full chip tapeout experience based on 7nm and lower technologies is highly preferred. Good problem solver. Self starter who can work independently. Experienced in working in a global team and dynamic environment. Ability to learn and adapt to new tools and methodologies on the fly. Excellent communication skills. Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must. Should have worked on tape out of at least 1-2 ASIC s in 7nm or lower technologies Education and Experience required: BS in Electrical Engineering/ Computer Engineering or related field and 8 years of related experience or an MS in Electrical Engineering/ Computer Engineering or related field and 6 years of related experience. Compensation and Benefits The annual base salary range for this position is USD 121,900.00 To USD 195,000.00 As a valued member of our team, you ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company s growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Requirements

Must-haves

If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)
If you already have a Candidate Account, please Sign-In before you apply.
In this role, the candidate will apply Broadcom s proven design methodology and milestone flow to meet Broadcom s rigorous criteria for achieving Right-first time silicon.
Primary expertise in place and route and/ or timing (constraints, STA) can be considered for this position.
Extremely proficient in design implementation activities both at block and SoC level.
Well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification and/ or constraints development, constraints validation, timing analysis and closure.
Experience with formal verification, timing analysis and Eco implementation.
Experience with tools such as Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime etc is highly desirable.
Good problem solver.
Self starter who can work independently.
Experienced in working in a global team and dynamic environment.
Ability to learn and adapt to new tools and methodologies on the fly.
Excellent communication skills.
Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must.
Should have worked on tape out of at least 1-2 ASIC s in 7nm or lower technologies
BS in Electrical Engineering/ Computer Engineering or related field and 8 years of related experience or an MS in Electrical Engineering/ Computer Engineering or related field and 6 years of related experience.

Nice-to-haves

Full chip tapeout experience based on 7nm and lower technologies is highly preferred.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)