Job description

Change the world. Love your job. Texas Instruments is seeking a Layout Design Manager. In this role, you will be leading a team developing power management ICs for high power density applications. This role combines people leadership with strong ownership of layout execution, while also adopting and driving new tools and flows across the team. You’ll also have opportunities to work with advanced power packages and help push the boundaries of thermal and electrical performance in cutting-edge power solutions. Technical qualifications • Deep understanding of analog and power layout techniques, including matching, symmetry, current density, electromigration, and IR drop management • Experience with high-voltage design rules, isolation techniques, and device spacing for BCD/HV processes • Strong knowledge of parasitic-aware layout for sensitive analog blocks such as bandgaps, references, comparators, and op-amps • Familiarity with power device layout, including LDMOS, power MOSFETs, bond pads, and ESD structures • Proficiency with layout tools such as Cadence Virtuoso and verification flows including DRC, LVS, PEX, and parasitic extraction • Knowledge of packaging considerations, including bond wire, flip-chip, and bump layout, as they relate to PMIC layout Leadership and collaboration qualifications • Ability to manage schedules, resource allocation, and cross-functional coordination across design, product, process, reliability, and packaging teams • Strong verbal and written communication skills for interfacing effectively with circuit designers, product engineers, and foundry partners • Experience mentoring and developing junior layout engineers • Demonstrated interpersonal, analytical, and problem-solving skills, with the ability to collaborate effectively across functions • Ability to quickly ramp on new systems and processes, take initiative, and drive results with strong time management and on-time delivery

Requirements

Must-haves

Change the world. Love your job.
Technical qualifications
Deep understanding of analog and power layout techniques, including matching, symmetry, current density, electromigration, and IR drop management
Experience with high-voltage design rules, isolation techniques, and device spacing for BCD/HV processes
Strong knowledge of parasitic-aware layout for sensitive analog blocks such as bandgaps, references, comparators, and op-amps
Familiarity with power device layout, including LDMOS, power MOSFETs, bond pads, and ESD structures
Proficiency with layout tools such as Cadence Virtuoso and verification flows including DRC, LVS, PEX, and parasitic extraction
Knowledge of packaging considerations, including bond wire, flip-chip, and bump layout, as they relate to PMIC layout
Leadership and collaboration qualifications
Ability to manage schedules, resource allocation, and cross-functional coordination across design, product, process, reliability, and packaging teams
Strong verbal and written communication skills for interfacing effectively with circuit designers, product engineers, and foundry partners
Experience mentoring and developing junior layout engineers
Demonstrated interpersonal, analytical, and problem-solving skills, with the ability to collaborate effectively across functions
Ability to quickly ramp on new systems and processes, take initiative, and drive results with strong time management and on-time delivery

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: oracle-cloud
Effort: medium