Job description

Job Details: Job Description: About the Team Logic Technology Development (LTD) is Intel Foundry s advanced technology engine, responsible for inventing, developing, and industrializing the process technologies that power future semiconductor products. From breakthrough device architectures and materials innovation to production-ready manufacturing solutions, LTD transforms research into customer-ready technologies that enable industry-leading performance at scale. About the Role The Lithography Overlay Principal Engineer is responsible for overlay control innovation, defining key technology roadmaps, and leading complex technical projects to establish Intel s overlay leadership. As a lithography overlay expert and technologist, you will be responsible for customization and addition of new features to base technologies to use in high volume manufacturing. Your expertise will focus on all aspects of improving overlay control. Responsibilities: LTD Principal Engineers are responsible for leading scientific research enabling the manufacture of innovative device architectures but not limited to: Lead scientific research enabling the manufacture of innovative device architectures coupled with the realization of these architectures. Designing, executing, and analyzing experiments necessary to meet engineering specifications for their process. Participate in the development of intellectual property. Integrate the many individual steps necessary for the manufacture of complex microprocessors. Ramp to manufacturing volumes to demonstrate the technology meets requirements while simultaneously transferring the technology to counterparts in manufacturing via the Copy Exactly Methodology. Provide technical guidance and mentorship to junior engineers and researchers, fostering a culture of continuous learning and development. Drive the development and implementation of customized, cost-effective, competitive, overlay solutions, ensuring compatibility with Intel s existing manufacturing processes and platforms. Provide technical guidance and mentorship to junior engineers and researchers, fostering a culture of continuous learning and development. Stay updated with industry trends, emerging technologies, and customer needs to inform customization strategies and identify opportunities for improvement. Required Skills and Experience Deep experience in lithography Broad experience in logic technology development, enhancement, and customization Current experience in advanced node overlay development processes. Proven ability to troubleshoot process impacts on overlay mark performance. Experience with integrated process development to co-optimize process flows and overlay mark design. Demonstrated proficiency in Design of Experiments (DOE), Statistical Process Control (SPC), and data analysis. Leadership skills with the ability to lead cross-functional teams and drive collaboration. Communication skills, both verbal and written, with the ability to convey complex technical concepts effectively. Preferred Skills and Experience Experience driving integrated process change methodologies based on overlay impact analysis. Direct overlay equipment development experience and vendor engagement. Hands-on experience with ASML EUV and DUV scanner platforms. Strong capability to troubleshoot complex process and production issues at advanced nodes. Deep working knowledge of lithography equipment operation, including automation and process control systems. Familiarity with factory automation or manufacturing execution and control systems. Qualifications: Degree in in Materials Science, Chemical Engineering, Chemistry, Physics, Mechanical Engineering, Electrical Engineering, or a related STEM discipline. Bachelor s degree with 12 years, Master s degree with 10 years, or Ph.D. with 7 years of experience. 7 years of hands-on lithography experience. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $211,400.00-298,440.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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Must-haves

Job Description: About the Team
The Lithography Overlay Principal Engineer is responsible for overlay control innovation, defining key technology roadmaps, and leading complex technical projects to establish Intel s overlay leadership.
LTD Principal Engineers are responsible for leading scientific research enabling the manufacture of innovative device architectures but not limited to:
Lead scientific research enabling the manufacture of innovative device architectures coupled with the realization of these architectures.
Designing, executing, and analyzing experiments necessary to meet engineering specifications for their process.
Participate in the development of intellectual property.
Integrate the many individual steps necessary for the manufacture of complex microprocessors.
Ramp to manufacturing volumes to demonstrate the technology meets requirements while simultaneously transferring the technology to counterparts in manufacturing via the Copy Exactly Methodology.
Provide technical guidance and mentorship to junior engineers and researchers, fostering a culture of continuous learning and development.
Drive the development and implementation of customized, cost-effective, competitive, overlay solutions, ensuring compatibility with Intel s existing manufacturing processes and platforms.
Provide technical guidance and mentorship to junior engineers and researchers, fostering a culture of continuous learning and development.
Stay updated with industry trends, emerging technologies, and customer needs to inform customization strategies and identify opportunities for improvement.
Required Skills and Experience
Deep experience in lithography
Broad experience in logic technology development, enhancement, and customization
Current experience in advanced node overlay development processes.
Proven ability to troubleshoot process impacts on overlay mark performance.
Experience with integrated process development to co-optimize process flows and overlay mark design.
Demonstrated proficiency in Design of Experiments (DOE), Statistical Process Control (SPC), and data analysis.
Leadership skills with the ability to lead cross-functional teams and drive collaboration.
Communication skills, both verbal and written, with the ability to convey complex technical concepts effectively.
Experience driving integrated process change methodologies based on overlay impact analysis.
Direct overlay equipment development experience and vendor engagement.

Nice-to-haves

Preferred Skills and Experience

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