Senior Principal Digital Design Engineer at MaxLinear

Job description

MaxLinear is seeking a Senior Principal Digital Design Engineer to join our team. In this role, you will focus on the following: • Define microarchitecture for complex subsystems (e.g., 200/400G 802.3, PCIe 6/7, DSP, FEC, data compression, AI/HW accelerators) • Analyze standards (PCI-SIG, IEEE 802.3, UALink, etc) and translate into implementable RTL • Work with cross-functional project teams (DV, PD, System/Firmware) to define product specifications (PPA), system architecture, HW/SW partitioning, and execution plan • Lead improvements to design methodology to maximize efficiency and predictability • RTL implementation in SystemVerilog of communication/DSP/packet-processing functions • Block-level verification including creation of Verilog or UVM testbenches • System-level verification in UVM+SysC environments including test case creation/debug, functional coverage specification, and code coverage analysis • Perform preliminary synthesis and power estimation, including SDC constraint specification and vector-driven power analysis • Perform design quality checks including lint, CDC and DFT-readiness checks • Support emulator-based verification including debug of SW driven test cases • Post silicon bring-up support and debug in lab; support system integration and production testing • Provide technical leadership in the ASIC design team to develop and productize next generation communication and data center SoCs • Expert in digital design including micro-architecture definition and area/power/timing optimization • Solid understanding of high-speed interfaces (Ethernet/PCIe), particularly MAC/PCS (or Transaction/Data Link/PHY logical) layers, and associated clocking, reset, and CDC considerations • Experience with performance modeling and analysis, including performance constraint identification and optimization • Extensive experience with ASIC front-end design flow including RTL coding (SystemVerilog), directed/randomized verification, simulation/emulation debug, lint/CDC checks, synthesis, power analysis and timing closure support • Knowledge of communications/DSP/FEC algorithms and experience with power/area efficient fixed-point ASIC implementation a plus • Familiar with SoC integration, including clock/reset architecture, bus protocols, embedded CPUs • Strong logical and creative problem-solving skills with excellent analytical and debugging skills • Solid written and verbal communication skills • Flexibility to ramp quickly on new technologies, products, and methodologies • Self-motivated with ability to provide leadership and work effectively in fast-paced environment • BS in Electrical Engineering or related + 11 years of experience, or MS + 9 years of experience, or Ph.D. + 6 years of experience MaxLinear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation. MaxLinear's good faith estimate starting base salary range is: $ 186,000 to $228 ,000 Annually We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off. The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience. Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status. MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world’s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world’s most challenging communication technology problems in the most efficient and effective manner. MaxLinear began by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we’ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we’ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel’s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers’ needs. Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore. We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market. We can recommend jobs specifically for you! Click here to get started.

Requirements

Must-haves

MaxLinear is seeking a Senior Principal Digital Design Engineer to join our team. In this role, you will focus on the following:
Define microarchitecture for complex subsystems (e.g., 200/400G 802.3, PCIe 6/7, DSP, FEC, data compression, AI/HW accelerators)
Analyze standards (PCI-SIG, IEEE 802.3, UALink, etc) and translate into implementable RTL
Work with cross-functional project teams (DV, PD, System/Firmware) to define product specifications (PPA), system architecture, HW/SW partitioning, and execution plan
Lead improvements to design methodology to maximize efficiency and predictability
RTL implementation in SystemVerilog of communication/DSP/packet-processing functions
Block-level verification including creation of Verilog or UVM testbenches
System-level verification in UVM+SysC environments including test case creation/debug, functional coverage specification, and code coverage analysis
Perform preliminary synthesis and power estimation, including SDC constraint specification and vector-driven power analysis
Perform design quality checks including lint, CDC and DFT-readiness checks
Support emulator-based verification including debug of SW driven test cases
Post silicon bring-up support and debug in lab; support system integration and production testing
Provide technical leadership in the ASIC design team to develop and productize next generation communication and data center SoCs
Expert in digital design including micro-architecture definition and area/power/timing optimization
Solid understanding of high-speed interfaces (Ethernet/PCIe), particularly MAC/PCS (or Transaction/Data Link/PHY logical) layers, and associated clocking, reset, and CDC considerations
Experience with performance modeling and analysis, including performance constraint identification and optimization
Familiar with SoC integration, including clock/reset architecture, bus protocols, embedded CPUs
Strong logical and creative problem-solving skills with excellent analytical and debugging skills
Solid written and verbal communication skills
Flexibility to ramp quickly on new technologies, products, and methodologies
Self-motivated with ability to provide leadership and work effectively in fast-paced environment
BS in Electrical Engineering or related + 11 years of experience, or MS + 9 years of experience, or Ph.D. + 6 years of experience
Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore.

Nice-to-haves

Knowledge of communications/DSP/FEC algorithms and experience with power/area efficient fixed-point ASIC implementation a plus

Application prep

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Keywords to mirror

Platform: icims
Effort: medium

Benefits

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Vision

401k

Paid Time Off