Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. TH E ROLE: Our CAD team delivers automated environments for industry-leading methodologies for 3D IC stack and advanced packaging design. Our flows encompass 3D netlist and physical design, advanced packaging implementation, and 3D analysis across EMIR, PERC/ESD, physical verification, and STA. 3D design and advance packaging complexity continue in increase. AMD designs are complex heterogeneous systems requiring a mix of specialized in-house capabilities while leveraging best in class EDA vendor solutions. This role is part of a global CAD team working in concert with mulitple design teams. You will collaborate directly with project teams to understand design requirements and deliver innovative solutions. The ideal candidate brings a strong silicon hardware design background, scripting proficiency, and hands-on experience applying machine learning to CAD or EDA workflows. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and the automation that makes it scale. You are energized by the intersection of AI and CAD — whether that means applying ML models to improve QoR, building LLM-assisted flows, or designing agentic systems that reduce manual iteration. You are a team player with excellent communication skills, comfortable collaborating across sites and time zones, and eager to take on hard, open-ended problems. PREFERRED EXPERIENCE: • Strong understanding of industry EDA tools, with emphasis on place-and-route, extraction, and analysis tools (e.g., ICC2, Innovus, Primetime, etc.). • Familiarity with chip- or system-level netlists and ability to debug connectivity across industry-standard formats (DEF/LEF/SPEF/Verilog/UPF/OAS/GDS). • Exposure with system level design verification processes including LEC, LVS, DRC, etc. • Comfort navigating large datasets and utilizing automation, distributed and cloud compute environments. • Demonstrated experience applying AI (ML-based optimization, LLM-assisted automation, agentic frameworks) to CAD, EDA, or hardware design problems. • Strong scripting skills in Python, TCL, and Perl within a Linux/Unix environment. • Experience with advanced-node tapeouts across silicon technologies. • Exposure to Advanced Packaging technologies preferred (2.5D, 3D, 3.5D, including interposers and silcion bridges). • Exposure to chip-level construction (PDN, bump planning) and analysis a plus. • Excellent verbal and written communication skills. KEY RESPONSIBILITIES: • Implement and maintain 3D-IC and advanced packaging design flows from RTL through signoff. • Lead hands-on debug and automation involving large chip level physical and logical netlists. • Partner with EDA vendors (Synopsys, Cadence) on 3D-IC feature requirements, enhancement requests, and AI co-development opportunities. • Partake in deep-dive discussions to provide guidelines to various organizations across AMD. • Develop and integrate end-to-end AI capabilities into CAD flows — including ML-based optimization, predictive modeling, and LLM-assisted automation. • Define strategy and key initiatives to ensure flows meet future design requirements and advanced technology nodes. • Regress methodology, analyze results, and develop capabilities that measurably improve quality of results. • Work closely with design and CAD implementation teams to deliver tools and flows meeting key QoR metrics: Timing, Area, and Performance. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Austin, TX This role is not eligible for visa sponsorship. #LI-SL3 Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Requirements

Must-haves

ADVANCE YOUR CAREER. ADVANCE THE WORLD.
Implement and maintain 3D-IC and advanced packaging design flows from RTL through signoff.
Lead hands-on debug and automation involving large chip level physical and logical netlists.
Partner with EDA vendors (Synopsys, Cadence) on 3D-IC feature requirements, enhancement requests, and AI co-development opportunities.
Partake in deep-dive discussions to provide guidelines to various organizations across AMD.
Develop and integrate end-to-end AI capabilities into CAD flows — including ML-based optimization, predictive modeling, and LLM-assisted automation.
Define strategy and key initiatives to ensure flows meet future design requirements and advanced technology nodes.
Regress methodology, analyze results, and develop capabilities that measurably improve quality of results.
Work closely with design and CAD implementation teams to deliver tools and flows meeting key QoR metrics: Timing, Area, and Performance.
Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION: Austin, TX
Benefits offered are described: AMD benefits at a glance .
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.

Nice-to-haves

Strong understanding of industry EDA tools, with emphasis on place-and-route, extraction, and analysis tools (e.g., ICC2, Innovus, Primetime, etc.).
Familiarity with chip- or system-level netlists and ability to debug connectivity across industry-standard formats (DEF/LEF/SPEF/Verilog/UPF/OAS/GDS).
Exposure with system level design verification processes including LEC, LVS, DRC, etc.
Comfort navigating large datasets and utilizing automation, distributed and cloud compute environments.
Demonstrated experience applying AI (ML-based optimization, LLM-assisted automation, agentic frameworks) to CAD, EDA, or hardware design problems.
Strong scripting skills in Python, TCL, and Perl within a Linux/Unix environment.
Experience with advanced-node tapeouts across silicon technologies.
Exposure to Advanced Packaging technologies preferred (2.5D, 3D, 3.5D, including interposers and silcion bridges).
Exposure to chip-level construction (PDN, bump planning) and analysis a plus.
Excellent verbal and written communication skills.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aimachine learningmlllmpython

Platform: amd
Effort: medium