Job description

As a CPU Implementation Feasibility Engineer you will be working extensively with micro architects to help define the CPU and memory subsystem and performing feasibility experiments. Responsibilities also include but are not limited to: -Performing different feasibility experiments for RTL innovations and improvements that drive the next generation high performance and low power chips -Making area, frequency, performance and power trade-offs -Driving RTL-to-GDS flow through synthesis/place-and-route with ambitious goals for power, performance, and area -Working with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, power, testability, and reliability -Performing different floor planning experiments to understand the microarchitectural feasibility for achieving high targets for performance, power and area BS and 10+ years of relevant industry experience Experience with VLSI implementation on high performance designs Deep knowledge of CPU microarchitecture Experience with critical path closure techniques Understanding of static timing analysis and power Physical Design Fundamentals Implementation experience on high performance CPU designs Understanding of low power microarchitecture and implementation techniques for CPUs Experience with Logical Equivalence checking (LEC) tools Experience with Power analysis tools Experience with Static Timing Analysis Tools Deep understanding of power, performance and area tradeoffs Strong communication and ability to influence architectural decisions with data

Requirements

Must-haves

-Performing different feasibility experiments for RTL innovations and improvements that drive the next generation high performance and low power chips
-Making area, frequency, performance and power trade-offs
-Driving RTL-to-GDS flow through synthesis/place-and-route with ambitious goals for power, performance, and area
-Working with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, power, testability, and reliability
-Performing different floor planning experiments to understand the microarchitectural feasibility for achieving high targets for performance, power and area
BS and 10+ years of relevant industry experience
Experience with VLSI implementation on high performance designs
Deep knowledge of CPU microarchitecture
Experience with critical path closure techniques
Understanding of static timing analysis and power
Physical Design Fundamentals
Implementation experience on high performance CPU designs
Understanding of low power microarchitecture and implementation techniques for CPUs
Experience with Logical Equivalence checking (LEC) tools
Experience with Power analysis tools
Experience with Static Timing Analysis Tools
Deep understanding of power, performance and area tradeoffs
Strong communication and ability to influence architectural decisions with data

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: apple
Effort: medium