Sr. Design Verification Engineer - Digital
Semtech· enterprise· Internet· Sep 15, 2026 · 1mo ago
USA - San Diego, CA
Hybrid
Full-time
Senior
$130K–$200K
8+ years exp
Job description
Location: San Diego, CA (Hybrid)
Our Team:
Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing, communications, and industrial equipment. As our future market opportunities have increased in recent years, we have continued to invest in disruptive analog platforms and have created innovative new solutions for a wide range of leading edge products.
The Sensing Product Group located in our San Diego office has unique expertise in system level platform solutions for Sensing Products including Touch & Proximity. These are leading edge low power touch-interface solutions integrated with highly accurate ADCs for enhanced sensing performance. These ultra-small, feature-rich sensing systems are optimized for a wide range of battery-powered, portable applications such as smartphones, laptops, tablets, wearables, handheld devices and other consumer or ITA control applications.
Job Summary:
The Sr. Design Verification Engineer is responsible for developing and implementing verification plans for digital IP blocks, subsystems, and full integrated circuits within mixed-signal sensing products. The Sr. Design Verification Engineer will closely collaborate with system, digital & physical design, embedded firmware, analog, and cross functional teams.
The role also includes technical leadership, mentoring and supervision of junior verification engineers, pre-silicon validation, and support to silicon validation, production test and application engineers.
Responsibilities:
Define, develop and optimize comprehensive verification plans and test strategies for digital IP blocks, subsystems, and full integrated circuits in mixed-signal products. Work closely with design teams to understand micro-architecture and functional specifications. Create and maintain detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (30%)
Design and implement UVM testbench environments using SystemVerilog for digital IP blocks, subsystems, and full-chip verification. Perform block and chip-level RTL and gate-level verification of digital logic interfacing with analog peripherals via behavioral models provided by the analog team. Develop constrained-random verification environments, directed test cases, and reusable verification components (drivers, monitors, scoreboards, coverage models). Debug complex simulation failures and identify root causes in RTL or verification environments. Improve verification scalability and reuse across projects through environment enhancement and tool automation. Build and maintain regression infrastructure, continuous integration flows, and coverage tracking. (30%)
Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%)
Supervise and mentor junior verification engineers. (15%)
Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%)
Support silicon lab evaluation, performance characterization and debug. (5%)
Technical support to test, product and application engineers. (5%)
Minimum Qualifications:
8 years of industry experience in integrated circuit design verification (DV)
In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals.
Proficiency in SystemVerilog as a high-level verification language with strong UVM implementation skills, Verilog for RTL comprehension and gate-level debug, Python scripting for verification automation, and industry-leading EDA verification tools (Synopsys VCS, Cadence Xcelium, Siemens Questa).
Experience with standard hardware protocols (I2C, I3C, SPI, MIPI)
Strong analytical, synthesis and problem solving skills
Demonstration of technical leadership
Independent, self-motivated, rigorous, innovating, team player and able to follow through
Excellent verbal and written communication skills
B.S. or M.S. in Electrical or Computer Engineering
Desired Qualifications
Familiarity consuming analog behavioral models (SV-RNM, Verilog-AMS) provided by analog design teams to verify digital control logic and mixed-signal interfaces
Formal verification experience using JasperGold, Synopsys VC Formal, or equivalent (property checking, FSM verification, protocol compliance)
Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off experience using SpyGlass CDC, JasperGold CDC, or equivalent
Low-power verification experience including UPF/CPF for power domain management — relevant for battery-powered consumer applications
Lint and structural sign-off experience (SpyGlass Lint or equivalent)
Knowledge of system-level integration: digital hardware, embedded firmware, signal processing concepts
Experience with capacitive sensing, touch, or proximity ICs
The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.
All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.
We are proud to be an EEO employer M/F/D/V. We maintain a drug-free workplace.
A reasonable estimate of the pay range for this position is $130,000 - $200,000. There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee’s total compensation package.
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