Design Verification Manager
Semtech· enterprise· Internet· Oct 14, 2026 · 14d ago
USA San Diego CA
Hybrid
Full-time
Manager
$116K–$216K
10+ years exp
Job description
Location: San Diego, CA or San Jose, CA - Hybrid (Friday Remote)
Our Team:
Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing, communications, and industrial equipment. As our future market opportunities have increased in recent years, we have continued to invest in disruptive analog and mixed-signal platforms and have created innovative new solutions for a wide range of leading edge products.
The Sensing Product Group located in our San Diego office has unique expertise in system level platform solutions for Sensing Products including Touch & Proximity. These are leading edge low power touch-interface solutions integrated with highly accurate ADCs for enhanced sensing performance. These ultra-small, feature-rich sensing systems are optimized for a wide range of battery-powered, portable applications such as smartphones, laptops, tablets, wearables, handheld devices and other consumer or industrial/telecommunications/automotive (ITA) control applications.
Job Summary:
The Design Verification (DV) Manager is responsible for leading a verification team, developing and implementing verification plans for a variety of mixed-signal integrated circuit blocks and systems. The Design Verification Manager will closely collaborate with system, digital, firmware, analog, and cross-functional teams.
The role includes technical leadership, mentoring and supervision of verification engineers, reporting to engineering leadership and program management, and support to silicon validation, production test and application engineers.
Responsibilities:
Lead, mentor and develop a team of geographically distributed verification engineers across multiple projects. Manage verification team deliverables, quality, schedules, and resource allocation for concurrent projects.
Drive definition and implementation of comprehensive verification strategies, test plans for digital/mixed-signal integrated circuit designs at block and top levels. Work closely with design teams to understand micro-architecture and specifications. Direct detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews.
Manage design and implementation of complex testbenches using SystemVerilog and UVM methodology. Lead block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Improve verification scalability and portability from project to project by environment enhancement and tools automation. Establish and manage continuous integration, regression testing, scoreboards, monitors, and checkers.
Report to engineering leadership and program management. Track and report verification progress using quantitative metrics and coverage analysis. Identify and mitigate verification risks early.
Interface with system, digital hardware, embedded firmware, analog, and cross-functional teams.
Drive adoption of advanced verification methodologies, best practices and tool evaluation.
Technical support to silicon lab evaluation, test, product and application engineers.
Minimum Qualifications:
10 years of industry experience in integrated circuit design verification (DV)
B.S. or M.S. in Electrical or Computer Engineering
Experience leading, mentoring or informally managing engineers or projects
Strong analytical, synthesis and problem-solving skills
In-depth knowledge and experience in digital integrated circuit verification with MCU-based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, external IPs, and analog peripherals.
Proficiency in SystemVerilog as high-level verification language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Siemens, Cadence)
Demonstration of technical leadership
Independent, self-motivated, rigorous, innovative, team player and able to follow through
Excellent verbal and written communication skills
Desired Qualifications:
Knowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modeling, test and application
Experience with standard hardware protocols (I2C, I3C, SPI, MIPI)
Experience in mixed-signal products, design and analog/mixed-signal (AMS) verification.
Experience with analog block behavioral modeling with SV RNM/Verilog/VHDL
Experience with consumer and/or ITA market circuit developments
The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.
All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.
We are proud to be an EEO employer M/F/D/V. We maintain a drug-free workplace.
A reasonable estimate of the base pay range for this position is USD $116,000 - $216,000. There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee’s total compensation package.
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