Job description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Advanced Packaging Design team is responsible for supporting customers with package solutions that meet challenging electrical requirements. High speed signaling and complex power delivery networks require new and custom solutions to meet constantly advancing application needs. Many of the new designs require multi-chip and multiple component configurations with high-speed IP requirements. In addition, our team is advancing Marvell's expertise in 3D packaging, Co-packaged optics and cutting-edge substrate materials. We work with the world's leading manufacturers to solve our client's most challenging designs and integrations with industry-leading packaging techniques. What You Can Expect We are looking for an experienced engineer to join our Advanced Packaging Design team in Burlington, VT as a Package Design Verification Specialist. In this role, you will be the gatekeeper of design quality, responsible for running critical verification flows including DRC, LVS and DFM. A core focus of this position is driving process refinement and efficiency. You will champion a shift-left approach, integrating physical design validation earlier into the development cycle to catch errors sooner, accelerate time-to-market, and optimize overall design execution, while also executing and owning physical verification of package designs. We are looking for an engineer who wants to step up and own process improvement and execution on product. In this role, you will be running DRC, LVS, and DFM while actively executing physical design validation workflows to help our design team catch errors long before final tape-out Key Responsibilities Physical Verification Execution: Own and execute comprehensive PKG floor-planning Checks, DRC (Design Rule Checking), LVS (Layout Versus Schematic), and DFM (Design for Manufacturability) flows for complex, multi-die advanced packaging architectures. Shift-Left Methodology: Refine and optimize engineering workflows by implementing automated validation checkpoints early in the design cycle to minimize late-stage layout iterations. Process Optimization: Identify bottlenecks in the current verification pipeline and help develop automated scripts, custom methodologies, or enhanced design kits to boost layout efficiency. Cross-Functional Collaboration: Partner closely with Package Architects, Physical Layout Designers, and Supply Partners to resolve complex violation reports and interpret cutting-edge foundry design rules. Documentation & Training: Author clear engineering documentation for newly established verification processes and train other members on these methodologies. What We re Looking For Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, and 3 years of experience in semiconductor design or manufacturing roles Technical Expertise: Proven experience driving quality improvement, design or process validation. Strong analytical mindset with a passion for finding structural gaps in engineering workflows. Excellent communication skills to bridge the gap between R&D architects, layout designers, tool vendors, and external suppliers. Ability to work in a fast-paced, highly collaborative R&D environment. Automation & Scripting: Strong scripting skills (TCL, Python, Perl, or Skill) to execute and automate verification tasks and data analysis. The ideal candidate will have the following experience, though not strictly required in order to be considered for the position: Running and debugging DRC, LVS, and DFM on complex silicon or packaging layouts. Experience with industry-standard physical verification tools (e.g., Siemens Calibre, Synopsys IC Validator, or Cadence Pegasus). Advanced Packaging Knowledge: Familiarity with advanced packaging technologies (e.g., 2.5D/3D IC, Chiplets, CoWoS, silicon interposers, or high-density fan-out architecture). Expected Base Pay Range (USD) 0 - 0, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps marvell.com . Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-MM1

Requirements

Must-haves

Shift-Left Methodology: Refine and optimize engineering workflows by implementing automated validation checkpoints early in the design cycle to minimize late-stage layout iterations.
Process Optimization: Identify bottlenecks in the current verification pipeline and help develop automated scripts, custom methodologies, or enhanced design kits to boost layout efficiency.
Cross-Functional Collaboration: Partner closely with Package Architects, Physical Layout Designers, and Supply Partners to resolve complex violation reports and interpret cutting-edge foundry design rules.
Documentation & Training: Author clear engineering documentation for newly established verification processes and train other members on these methodologies.
What We re Looking For
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, and 3 years of experience in semiconductor design or manufacturing roles
Proven experience driving quality improvement, design or process validation.
Strong analytical mindset with a passion for finding structural gaps in engineering workflows.
Excellent communication skills to bridge the gap between R&D architects, layout designers, tool vendors, and external suppliers.
Ability to work in a fast-paced, highly collaborative R&D environment.
Automation & Scripting: Strong scripting skills (TCL, Python, Perl, or Skill) to execute and automate verification tasks and data analysis.
The ideal candidate will have the following experience, though not strictly required in order to be considered for the position:
Running and debugging DRC, LVS, and DFM on complex silicon or packaging layouts.
Experience with industry-standard physical verification tools (e.g., Siemens Calibre, Synopsys IC Validator, or Cadence Pegasus).
Advanced Packaging Knowledge: Familiarity with advanced packaging technologies (e.g., 2.5D/3D IC, Chiplets, CoWoS, silicon interposers, or high-density fan-out architecture).
0 - 0, $ per annum
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps marvell.com .
Interview Integrity

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipython

Platform: workday
Effort: long