Job description

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years in the trenches of physical design, where the difference between a chip that tapes out on schedule and one that doesn't often come down to a timing path you caught or a methodology decision you made six months earlier. You know that getting to signoff is not about running tools, it is about understanding what the data is telling you and building flows that make the next iteration faster and smarter. You are the engineer who looks at a timing report and sees patterns, not just violations. When a clock tree is misbehaving or a design is bleeding power, you do not just fix the symptom, you trace it back to the root cause and build something that prevents it from happening again. Automation is not a buzzword to you, it is how you scale yourself across multiple projects without losing quality. You have worked at advanced nodes where margins are thin and every decision counts. You know your way around ICC2 or Fusion Compiler well enough that you can tell when the tool is doing something unexpected, and you know how to script your way out of it. At Synopsys, you will work on real silicon with real constraints, and what you build will directly affect whether our customers can close their designs on time. What You'll Be Doing • Drive timing closure, signoff readiness, and PPA optimization for advanced-node customer designs, working across block, subsystem, and chip-level implementations • Develop and enhance physical design methodologies and automation solutions using TCL, Python, Perl, or Pandas to improve design quality, predictability, and team efficiency • Perform static timing analysis, clock-tree synthesis, and ECO implementation using tools like PrimeTime , ICC2, Fusion Compiler, or Cadence Innovus • Analyze design data and trends to identify bottlenecks, predict issues, and build flows that make the next tapeout smoother than the last • Collaborate with cross-functional engineering teams including design, verification, and CAD to ensure successful silicon delivery • Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve complex implementation challenges • Troubleshoot complex physical design problems that do not have obvious answers, and develop scalable technical solutions that work across multiple projects The Impact You Will Have • Your methodologies and automation will directly reduce design cycle time and improve first-pass silicon success for Synopsys customers building chips at 3nm, 2nm, and beyond • The flows you build will be reused across multiple projects and teams, multiplying your impact across dozens of tapeouts • Your timing closure expertise will help customers meet aggressive PPA targets that define whether their products succeed in the market • The design data analysis and trend identification you perform will shape how future tools and methodologies are developed at Synopsys • Your contributions to AI-driven design optimization will help define the next generation of physical implementation workflows • The technical solutions you develop will become reference methodologies that other engineers learn from and build upon • Your ability to troubleshoot complex corner cases will unblock critical customer programs and strengthen Synopsys relationships with leading semiconductor companies What You'll Need • Bachelor's or Master's degree in Electrical Engineering , Computer Engineering, or a related technical field • 5+ years of hands-on experience with ASIC physical design, implementation, and timing closure across block, subsystem, or chip-level designs • Deep working knowledge of static timing analysis, clock-tree synthesis, signoff flows, and ECO methodologies • Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus • Strong scripting and automation skills using TCL, Python, Perl, or similar languages to build flows and analyze data • Experience with advanced-node semiconductor design at 7nm or below is a strong plus • Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows is a plus Who You Are • You can look at a timing report with 10,000 violations and quickly identify the three things that actually matter , then explain your reasoning to a design lead in a way that gets buy-in • When a flow is not working, you do not wait for someone else to fix it, you dig into the logs, trace the problem, and script a solution that works for the whole team • You are comfortable working independently across a global organization, coordinating with teams in different time zones without losing momentum or context • You know the difference between a quick fix that gets you through today and a methodology change that prevents the problem from coming back, and you have the judgment to choose the right approach for the situation • You stay current with what is happening at the leading edge of physical design, whether that is new tool capabilities, emerging process nodes, or AI-driven optimization techniques • You are an excellent problem solver who treats complex implementation challenges as puzzles worth solving, not obstacles to complain about The Team You'll Be Part Of Your recruiter will share more about the team structure and mission during the interview process. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Requirements

Must-haves

What You'll Be Doing
Drive timing closure, signoff readiness, and PPA optimization for advanced-node customer designs, working across block, subsystem, and chip-level implementations
Develop and enhance physical design methodologies and automation solutions using TCL, Python, Perl, or Pandas to improve design quality, predictability, and team efficiency
Perform static timing analysis, clock-tree synthesis, and ECO implementation using tools like PrimeTime , ICC2, Fusion Compiler, or Cadence Innovus
Analyze design data and trends to identify bottlenecks, predict issues, and build flows that make the next tapeout smoother than the last
Collaborate with cross-functional engineering teams including design, verification, and CAD to ensure successful silicon delivery
Contribute to AI-assisted and machine learning-driven design optimization initiatives, applying data-driven approaches to solve complex implementation challenges
Troubleshoot complex physical design problems that do not have obvious answers, and develop scalable technical solutions that work across multiple projects
The Impact You Will Have
Your methodologies and automation will directly reduce design cycle time and improve first-pass silicon success for Synopsys customers building chips at 3nm, 2nm, and beyond
The flows you build will be reused across multiple projects and teams, multiplying your impact across dozens of tapeouts
Your timing closure expertise will help customers meet aggressive PPA targets that define whether their products succeed in the market
The design data analysis and trend identification you perform will shape how future tools and methodologies are developed at Synopsys
Your contributions to AI-driven design optimization will help define the next generation of physical implementation workflows
The technical solutions you develop will become reference methodologies that other engineers learn from and build upon
Your ability to troubleshoot complex corner cases will unblock critical customer programs and strengthen Synopsys relationships with leading semiconductor companies
What You'll Need
Bachelor's or Master's degree in Electrical Engineering , Computer Engineering, or a related technical field
5+ years of hands-on experience with ASIC physical design, implementation, and timing closure across block, subsystem, or chip-level designs
Deep working knowledge of static timing analysis, clock-tree synthesis, signoff flows, and ECO methodologies
Proficiency with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, or Cadence Innovus
Strong scripting and automation skills using TCL, Python, Perl, or similar languages to build flows and analyze data
Experience with advanced-node semiconductor design at 7nm or below is a strong plus

Nice-to-haves

Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows is a plus

Application prep

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Keywords to mirror

aipythonmachine learning

Platform: avature
Effort: medium

Benefits

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Pto

Wellness