Job description

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent your career at the boundary where theory meets reality, where a beautifully designed circuit either performs exactly as modeled or reveals something nobody saw coming. You live for that moment when the oscilloscope trace tells you what the simulation missed, and you know how to chase that signal until you understand why. Lab work energizes you. Setting up a test fixture, probing a board, watching a high-speed eye diagram open up after hours of debugging, that is where you do your best thinking. You are comfortable translating between the analog designers who built the circuit and the test data that proves whether it works. When something does not behave as expected, you do not just log a bug, you dig into the circuit, the board, the test setup, and the protocol until you find the actual root cause. You know your way around FPGAs, scripting environments, and lab equipment that costs more than a car. Working across disciplines does not intimidate you, it is just how the work gets done. At Synopsys, you will validate SerDes PHYs that power the systems running the world, and the lab you work in will have the tools to do it right. What You'll Be Doing • Test silicon implementations of high-speed SerDes PHYs using state-of-the-art lab equipment including oscilloscopes, network analyzers, and signal integrity tools • Debug silicon behavior and supporting hardware when test results do not match expectations, tracing issues across the analog circuit, test board, and measurement setup • Run characterization tests across PVT corners and operating conditions, then create detailed test reports that communicate results to design and product teams • Design and build custom test boards and hardware solutions to support bring-up, debug, and characterization of new PHY IP • Program FPGAs in Verilog to generate test patterns, control interfaces, and automate test sequences for protocols like USB, PCIe, SATA, and Ethernet • Write test automation scripts in Python or MATLAB to streamline data collection, analysis, and reporting • Collaborate with analog designers to investigate circuit behavior, apply theoretical knowledge to explain performance limits, and validate design assumptions in silicon The Impact You Will Have • Validate SerDes PHY IP that ships in high-volume SoCs across automotive, data center, and consumer applications • Catch silicon issues early in the validation cycle, reducing time to market and preventing costly respins • Build reusable test infrastructure and automation that accelerates characterization for future product generations • Deliver test data and insights that directly inform design decisions, helping analog teams optimize performance, power, and area • Contribute to the quality and reliability of IP that powers communication interfaces in systems used by millions of people every day • Strengthen the feedback loop between silicon validation and design, making the entire R&D process faster and more predictable • Help establish best practices for high-speed validation in a world-class R&D lab environment What You'll Need • Bachelor's degree in Electrical Engineering or equivalent practical experience • Solid understanding of analog IC circuit design and behavior, especially in high-speed mixed-signal environments • Strong debugging skills with the ability to isolate issues across silicon, hardware, firmware, and test setup • Hands-on experience with lab equipment including oscilloscopes, network analyzers, signal generators, and power supplies • Software programming experience in MATLAB, Python, or similar environments for test automation and data analysis • FPGA programming knowledge using Verilog for test pattern generation and protocol control • Familiarity with high-speed interface protocols such as USB, PCI Express, SATA, or Ethernet is a strong plus • Experience with NRZ and PAM4 signaling, equalization techniques, or SerDes architecture is a plus • Knowledge of communication interfaces like JTAG, I2C, and SPI for device control and configuration Who You Are • You can look at a noisy eye diagram and quickly form hypotheses about whether the issue is jitter, crosstalk, impedance mismatch, or something in the circuit itself • You are methodical in your test approach but flexible enough to pivot when the data tells you something unexpected • You communicate clearly with people across disciplines, translating between the language of circuit designers, hardware engineers, and product teams without losing technical accuracy • You are comfortable working independently in the lab but know when to pull in a design engineer or a board specialist to solve a problem faster • You take ownership of your test setups and results, you do not hand off half-debugged data or blame the tools when something does not work • You stay current with high-speed design trends, new test methodologies, and emerging protocols because the technology moves and you want to move with it The Team You'll Be Part Of You will join an R&D team developing high-speed SerDes PHYs within Synopsys Silicon IP. The team includes analog designers and hardware engineers from diverse technical backgrounds, all focused on delivering best-in-class IP for next-generation SoCs. The R&D test lab is equipped with high-speed test equipment and supports a hands-on, collaborative engineering culture. You will work closely with design, product, and applications teams to ensure silicon meets performance targets and customer requirements. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Requirements

Must-haves

What You'll Be Doing
Test silicon implementations of high-speed SerDes PHYs using state-of-the-art lab equipment including oscilloscopes, network analyzers, and signal integrity tools
Debug silicon behavior and supporting hardware when test results do not match expectations, tracing issues across the analog circuit, test board, and measurement setup
Run characterization tests across PVT corners and operating conditions, then create detailed test reports that communicate results to design and product teams
Design and build custom test boards and hardware solutions to support bring-up, debug, and characterization of new PHY IP
Program FPGAs in Verilog to generate test patterns, control interfaces, and automate test sequences for protocols like USB, PCIe, SATA, and Ethernet
Write test automation scripts in Python or MATLAB to streamline data collection, analysis, and reporting
Collaborate with analog designers to investigate circuit behavior, apply theoretical knowledge to explain performance limits, and validate design assumptions in silicon
The Impact You Will Have
Validate SerDes PHY IP that ships in high-volume SoCs across automotive, data center, and consumer applications
Catch silicon issues early in the validation cycle, reducing time to market and preventing costly respins
Build reusable test infrastructure and automation that accelerates characterization for future product generations
Deliver test data and insights that directly inform design decisions, helping analog teams optimize performance, power, and area
Contribute to the quality and reliability of IP that powers communication interfaces in systems used by millions of people every day
Strengthen the feedback loop between silicon validation and design, making the entire R&D process faster and more predictable
Help establish best practices for high-speed validation in a world-class R&D lab environment
What You'll Need
Bachelor's degree in Electrical Engineering or equivalent practical experience
Solid understanding of analog IC circuit design and behavior, especially in high-speed mixed-signal environments
Strong debugging skills with the ability to isolate issues across silicon, hardware, firmware, and test setup
Hands-on experience with lab equipment including oscilloscopes, network analyzers, signal generators, and power supplies
Software programming experience in MATLAB, Python, or similar environments for test automation and data analysis
FPGA programming knowledge using Verilog for test pattern generation and protocol control

Nice-to-haves

Experience with NRZ and PAM4 signaling, equalization techniques, or SerDes architecture is a plus

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipython

Platform: avature
Effort: medium

Benefits

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