Job description

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and visionary ASIC Digital Architect , who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement new HPC Interface IP solutions used by leading semiconductor companies worldwide. What You’ll Be Doing: • Defining and developing ASIC RTL design and verification at both chip and block levels. • Creating and executing design plans for complex digital designs, focusing on high-speed IO protocols including DDR, PCIe, CXL, UCIe, and Ethernet technologies. • Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. • Utilizing advanced design and verification methodologies and tools to achieve high-quality results. • Mentoring engineers and promoting best practices, technical excellence, and continuous improvement. • Communicating with internal and external stakeholders to align goals and deliverables. The Impact You Will Have: • Enhancing the reliability and performance of Synopsys’ digital design processes. • Advancing DDR, PCIe, UCIe, and Ethernet technologies to enable cutting-edge semiconductor solutions. • Improving time-to-market for high-performance silicon chips through efficient methodologies. • Building and nurturing a highly skilled development team, elevating overall project quality. • Influencing strategic decisions that shape the future of Synopsys’ capabilities. • Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You’ll Need: • BSEE/MSEE with extensive experience in ASIC RTL design. • In-depth knowledge of DDR, PCIe, UCIe, and Ethernet technologies and similar IO protocols and their applications. • Proficiency in advanced digital design tools and methodologies. • Strong problem-solving skills and the ability to work independently. • Excellent communication skills for effective collaboration with diverse teams. Who You Are: • A visionary leader with a strategic mindset. • A mentor who fosters talent and encourages innovation. • A proactive problem solver who thrives in complex environments. • An effective communicator with the ability to convey technical concepts to a broad audience. • A team player who values collaboration and diversity. The Team You’ll Be A Part Of: You’ll join a high-impact Synopsys team advancing next-generation design technologies. In this role, you will help shape the architecture and execution of leading digital core protocols—including DDR, PCIe, UCIe and Ethernet technologies—driving innovation, integration, and performance across critical semiconductor solutions. Rewards and Benefits: Synopsys offers a comprehensive package of health, wellness, financial, and professional development benefits designed to support you throughout your career. #LI-SW1 At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Requirements

Must-haves

Defining and developing ASIC RTL design and verification at both chip and block levels.
Creating and executing design plans for complex digital designs, focusing on high-speed IO protocols including DDR, PCIe, CXL, UCIe, and Ethernet technologies.
Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.
Utilizing advanced design and verification methodologies and tools to achieve high-quality results.
Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
Communicating with internal and external stakeholders to align goals and deliverables.
Enhancing the reliability and performance of Synopsys’ digital design processes.
Advancing DDR, PCIe, UCIe, and Ethernet technologies to enable cutting-edge semiconductor solutions.
Improving time-to-market for high-performance silicon chips through efficient methodologies.
Building and nurturing a highly skilled development team, elevating overall project quality.
Influencing strategic decisions that shape the future of Synopsys’ capabilities.
Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.
BSEE/MSEE with extensive experience in ASIC RTL design.
In-depth knowledge of DDR, PCIe, UCIe, and Ethernet technologies and similar IO protocols and their applications.
Proficiency in advanced digital design tools and methodologies.
Strong problem-solving skills and the ability to work independently.
Excellent communication skills for effective collaboration with diverse teams.
A visionary leader with a strategic mindset.
A mentor who fosters talent and encourages innovation.
A proactive problem solver who thrives in complex environments.
An effective communicator with the ability to convey technical concepts to a broad audience.
A team player who values collaboration and diversity.
Synopsys offers a comprehensive package of health, wellness, financial, and professional development benefits designed to support you throughout your career. #LI-SW1

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: avature
Effort: medium

Benefits

Benefits detected in the listing.

Vision

Wellness

Professional Development